Skip to content

Port gHashTag/trinity:fpga/openxc7-synth/d_g22_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_g22 - #5757

Merged
gHashTag merged 3 commits into
masterfrom
queen-5748
Oct 4, 2026
Merged

gHashTag merged 3 commits into
masterfrom
queen-5748

Conversation

@gHashTag

@gHashTag gHashTag commented Oct 3, 2026

Copy link
Copy Markdown
Owner

Closes #5748

Written by a bee on queen-5748 and published by tools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.

1 file changed, 231 insertions(+)

🤖 Generated with Claude Code

Trinity Bee and others added 2 commits October 3, 2026 11:58
Create specs/port/trinity/fpga/openxc7-synth/d_g22_test.t27 as a trinity_top module
that replicates the original Verilog behavior: clock buffering with 24-bit counter
and active-low LED output driven by counter[23] inversion.

The module includes:
- Counter configuration and LED configuration structs
- Clock buffer simulation function
- Counter increment with wrap-around logic
- Bit extraction from counter value
- LED output computation with active-low support
- Comprehensive test suite covering all functionality
- Validation functions for configuration checking
- Performance benchmarks

All acceptance criteria met:
- File exists and contains trinity_top module
- Generated Verilog produces correct module
- File parses and compiles successfully
- Contains 14 passing tests
- No BLOCKED compilation errors

Closes #5748
A pull request must add exactly one docs/now entry and a bee has no way
to know that: its brief names a boundary file and acceptance criteria,
and docs/now/ is neither. The publisher adds it rather than failing the
gate.

Closes #5748

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
@github-actions

github-actions Bot commented Oct 3, 2026

Copy link
Copy Markdown
Contributor

📓 NotebookLM Notebook linked to this PR

This notebook contains session context, decisions, and artifacts for this work.

@github-actions

github-actions Bot commented Oct 3, 2026

Copy link
Copy Markdown
Contributor

PR Dashboard

Generated at: 2026-10-03 12:11:50 UTC

Summary

Status Count
Total Open PRs 41
PRs with Failing Checks 40
PRs with All Checks Green 1
READY 1
FAILING 40
PENDING 0
NO CHECKS YET 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=b45a356c2eb6 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

tools/queen/publish.py wrote `(published DATE)`, which
tools/check_now_entry_shape.py HEADING does not accept; fixed in
the publisher by #5777. Only the first line changes.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
@github-actions

github-actions Bot commented Oct 3, 2026

Copy link
Copy Markdown
Contributor

PR Dashboard

Generated at: 2026-10-03 17:48:00 UTC

Summary

Status Count
Total Open PRs 48
PRs with Failing Checks 24
PRs with All Checks Green 24
READY 0
FAILING 24
PENDING 0
NO CHECKS YET 0

These columns do not partition: 0 + 24 + 0 + 0 = 24, and there are 48 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=b45a356c2eb6 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@github-actions

github-actions Bot commented Oct 3, 2026

Copy link
Copy Markdown
Contributor

📓 NotebookLM Notebook linked to this PR

This notebook contains session context, decisions, and artifacts for this work.

This was referenced Oct 4, 2026
@gHashTag
gHashTag merged commit 3ab068c into master Oct 4, 2026
32 of 35 checks passed
@gHashTag
gHashTag deleted the queen-5748 branch October 4, 2026 17:38
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

bee-reviewed A reviewer bee reviewed and verified this PR at its current head; the only merge signal (#5525)

Projects

None yet

Development

Successfully merging this pull request may close these issues.

Port gHashTag/trinity:fpga/openxc7-synth/d_g22_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_g22_test.t27

2 participants