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feat(xilinx7): open prjxray-db digest, flow.t27 and a symmetric L3 bench (Closes #6068) - #6072

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feat(xilinx7): open prjxray-db digest, flow.t27 and a symmetric L3 bench (Closes #6068)#6072
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@dmitrii-f-t27 dmitrii-f-t27 commented Oct 4, 2026

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Closes #6068. Refs gHashTag/trinity#1272 (third box: the digest without the local helper).

What

  • specs/xilinx7/fasm_digest.py -- the prjxray-db digest bitwalk --fasm reads, from the Python standard library only.
  • specs/xilinx7/flow.t27 -- the arithmetic of the t27.ai/#/devkit flow table in integer ms (best/worst of N, replaced layer, saved, speedup and share half up, Amdahl ceiling, tenths of an hour a year, and a range verdict: faster only if the rewrite's slowest run beats the old tool's fastest). Sealed (.trinity/seals/xilinx7_xilinx7_flow.json).
  • conformance/xilinx7_flow.json -- 16 vectors, replayed by the new bitwalk --flow; bitwalk --flow-runs turns a runs file into the table, every number through flow.rs.
  • specs/xilinx7/l3_bench.py + .github/workflows/xilinx7-l3-bench.yml -- one runner, fasm2frames as openXC7 ships it (textX parser) and with fasm's antlr parser, xc7frames2bit, fpga-assembler fpga-as (pinned 50c18800) and bitwalk; N rotated runs each; .frames / .bit byte-compared before timing.
  • docs/now/2026-10-04-xilinx7-open-digest-and-l3-bench.md.

Checked

  • bitwalk --fasm + open digest vs the openXC7 image's fasm2frames: 42/42 xc7a200t AX7203 builds byte-identical (local, prjxray-db a90f27c1).
  • t27c test-report specs/xilinx7/flow.t27: 8/8 (zig 0.16.0). Mutation: 9 of 10 killed, 1 equivalent.
  • bitwalk --flow conformance/xilinx7_flow.json: 16/16; a wrong expectation turns it red.
  • t27c seal --save with ./target/release/t27c built in this tree; tools/check_json_parses.py, tools/ci/check_specs_still_parse.py (base merge-base) OK; tools/check_seal_coverage.py OK.
  • The bench numbers: from this PR's xilinx7 L3 bench run, added below when it is green.

🤖 Generated with Claude Code

@dmitrii-f-t27 @claude
feat(xilinx7): open prjxray-db digest, flow.t27 and a symmetric L3 be…
23ef2b0 
…nch (Closes #6068)

- specs/xilinx7/fasm_digest.py: the digest bitwalk --fasm reads, standard library only.
  bitwalk --fasm with it matches fasm2frames on 42/42 xc7a200t AX7203 builds.
- specs/xilinx7/flow.t27: the #/devkit flow arithmetic (best/worst of N, speedup, share,
  Amdahl ceiling, hours a year, range verdict); 8/8 tests, sealed; vectors in
  conformance/xilinx7_flow.json replayed by the new `bitwalk --flow`.
- specs/xilinx7/l3_bench.py + xilinx7-l3-bench workflow: fasm2frames (textX and antlr),
  xc7frames2bit, fpga-as and bitwalk, N rotated runs each, bytes compared first.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Generated at: 2026-10-04 13:09:09 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 40
PRs with All Checks Green 10
READY 9
FAILING 40
PENDING 0
NO CHECKS YET 0

These columns do not partition: 9 + 40 + 0 + 0 = 49, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=155b3c1e8693 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

This was referenced Oct 4, 2026
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@dmitrii-f-t27 @claude
fix(xilinx7): bench compares .bit from the sync word, keeps frame dif…
0f32e7e 
…fs; classify the workflow (Refs #6068)

- l3_bench.py: xc7frames2bit writes the frames path it was given into the .bit header, so
  every .bit now compares from the sync word on (bitwalk's also whole, given that header).
  The first CI run had all .frames equal for bitwalk and both fasm2frames parsers, and
  failed only on that header. Every tool is timed; one with other bytes is marked and its
  frame diff kept in bench.json. fpga-as wrote other .frames: that is what the diff is for.
- check_pr_branch_filters.py: xilinx7-l3-bench.yml is not merge-critical (it measures).
- Census moved: `tri census pin` quiet and shell, "workflow files read" 61 -> 62, because
  this PR adds .github/workflows/xilinx7-l3-bench.yml. Re-blessed here.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
@dmitrii-f-t27

dmitrii-f-t27 commented Oct 4, 2026

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spec-guards: red for a reason this PR does not touch. Its failing step reports ring-096-rust DRIFTED against specs/numeric/formats.t27 (f32_to_gf16, gf16_to_f32, ...), and spec-guards is red on master too (runs at 2e852cf, 0886f01, b1e3c15 on 2026-10-04). This PR changes no ring and no specs/numeric file. gate-topology and cli-tri are fixed in 0f32e7e; bench: see the same commit.

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Generated at: 2026-10-04 13:44:38 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 40
PRs with All Checks Green 10
READY 9
FAILING 40
PENDING 0
NO CHECKS YET 0

These columns do not partition: 9 + 40 + 0 + 0 = 49, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=a47525693295 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@dmitrii-f-t27

dmitrii-f-t27 commented Oct 4, 2026

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duplicate-bodies: not from this PR. The four groups it names (local_branch, nested_tail, ordinary_if, wide_tail) are in specs/compiler/rust_tail_returns.t27 and specs/compiler/verilog_branch_context.t27, both on master; the dupe-ratchet workflow is red on master at 2e852cf and 0886f01. On this branch alone (merge-base) tools/dupe_scan.py prints ok. This PR adds no function to either file.

This was referenced Oct 4, 2026
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@dmitrii-f-t27 @claude
fix(xilinx7): bench checks equivalence, not file identity, where the …
1a48ebe 
…format differs (Refs #6068)

The second CI run (runs 37206598855): bitwalk's .frames equal fasm2frames' and its .bit equals
xc7frames2bit's from the sync word on, on all 4 files. Two comparisons were wrong:
- bitwalk's whole-file .bit check lacked xc7frames2bit's header date and time; it now reads
  them from the reference header (checked locally: whole file identical).
- fpga-as --dump_frames_file is sparse (only the frames it wrote); bits_differ was 0 on the
  frames both have. Frames now also compare as nonzero sets, and a .bit with another stream
  is walked with `bitwalk --frames` to ask whether it loads the same frames.
`bitwalk --flow-runs` totals per stage (L3, L3+L4), each tool over the files it ran: the
previous single sum mixed the stages and gave fpga-as a false 145x.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
@dmitrii-f-t27 dmitrii-f-t27 mentioned this pull request Oct 4, 2026
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Generated at: 2026-10-04 14:37:36 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 42
PRs with All Checks Green 8
READY 7
FAILING 42
PENDING 0
NO CHECKS YET 0

These columns do not partition: 7 + 42 + 0 + 0 = 49, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=a47525693295 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@dmitrii-f-t27 @claude
feat(xilinx7): bench times L4 on its own too (Refs #6068)
b1113e5 
The L3+L4 sums of run 37206598855 imply bitwalk --write ~343 ms against xc7frames2bit
~244 ms per file, but only as a difference; L4 now gets its own runs so flow.t27's range
verdict can judge it.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Generated at: 2026-10-04 14:38:23 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 42
PRs with All Checks Green 8
READY 7
FAILING 42
PENDING 0
NO CHECKS YET 0

These columns do not partition: 7 + 42 + 0 + 0 = 49, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=a47525693295 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

This was referenced Oct 4, 2026
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@dmitrii-f-t27 @claude
Merge master into feat/xilinx7-l3-bench (Refs #6068)
1975b55 
Conflict in tools/census/shell.txt only, re-blessed on the merged tree with
`tri census pin --bless`. Census moved: shell "run: steps" 277 (this branch) /
270 (master) -> 278 and "the runner does" 256 / 249 -> 257, because master
changed loop-tools-gate.yml and pr-dashboard.yml and this branch adds
xilinx7-l3-bench.yml; "workflow files read" stays 62 (61 on master + this
branch's workflow).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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dmitrii-f-t27 enabled auto-merge (squash) October 4, 2026 16:30
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Generated at: 2026-10-04 16:32:17 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 45
PRs with All Checks Green 5
READY 4
FAILING 45
PENDING 0
NO CHECKS YET 0

These columns do not partition: 4 + 45 + 0 + 0 = 49, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=4a3d2f43c9f5 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@dmitrii-f-t27
dmitrii-f-t27 merged commit e0f894f into master Oct 4, 2026
23 of 25 checks passed
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xilinx7: open prjxray-db digest for bitwalk --fasm and a symmetric L3 benchmark (fasm2frames, fpga-assembler, bitwalk)

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