Master red after the 2026-10-04 batch merge: four ratchets back to green - #6221
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…reen - wasm-explorer.yml: `run: cargo test -- --skip compiler:: -p ...` is a plain scalar with ": " in it, so the file did not parse and gate-topology failed. Block scalar, and args in the right order: `cargo test -p t27-wasm-explorer -- --skip compiler::`. - duplicate-bodies: HirCoverPoint_validate, counter_24bit and is_counter_power_of_two recorded with `python3 tools/dupe_scan.py --bless` (+3 ledger lines, nothing else moved). - Corpus ratchet: eleven new conflicted type names from the FPGA and compiler.rs port specs added to docs/reports/type_conflicts.json in the exact shape `tri types ratchet --bless` writes, and each one read and classified (7 DRIFT, 4 DISTINCT) in type_conflicts_classified.json and docs/TYPE_CONFLICTS.md so `tri types classified` holds too. Refs #5776 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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This was referenced Oct 4, 2026
…en-verilog - gate-topology: once wasm-explorer.yml parses, check_pr_branch_filters.py reads it and counts it unclassified (24 -> 25 over a ceiling of 24). It is classified NOT_MERGE_CRITICAL with its reason; the ceiling holds at 24. - Corpus ratchet: with the type steps green the suite step ran for the first time since the batch and reported two UNEXPECTED FAILURES at gen-verilog, specs/port/scripts/tri-issue-create.t27 (#5755) and specs/port/trinity/src/vibeec/validation_engine.t27 (#5836): a local `[N][]const u8` string array, which the Verilog backend refuses (W469). Recorded under #5549 with the other ports to be redone; max_entries 111 -> 113 by hand, with the reason in _why_entries_rose. Refs #5776 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-10-04 18:13:24 UTC
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…ot diff read master's own gen/ change as this PR's) Refs #5776 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-10-04 18:28:46 UTC
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This was referenced Oct 4, 2026
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Master (
bae81aee2) went red on four non-required checks after the batch merge of ~46 PRs on 2026-10-04 17:20-17:45Z. Pre-batch master732f43990was red only on spec-guards and Scorecard, which this PR does not touch.Refs #5776
1. gate-topology -- fixed
wasm-explorer.yml: ScannerError: mapping values are not allowed here..github/workflows/wasm-explorer.ymlline 39,run: cargo test -- --skip compiler:: -p t27-wasm-explorer-- a plain YAML scalar containing:, so the workflow file does not parse (it also passed-pafter--, to the test binary).run: |block withcargo test -p t27-wasm-explorer -- --skip compiler::. Checked withpython3 -c "import yaml; yaml.safe_load(...)".scripts/ci/check_pr_branch_filters.pyreads it and finds it unclassified (24 -> 25 over a ceiling of 24).wasm-explorer.yml(added by Nothing builds bindings/wasm-explorer, which is how the artifact it replaces drifted in the first place #4489's workflow commit 9b6ddc2) is now inNOT_MERGE_CRITICALwith its reason; the ceiling holds at 24.2. duplicate-bodies -- fixed
HirCoverPoint_validate,counter_24bit,is_counter_power_of_twocopied twice, in no ledger.counter_24bitin d_bufg_test (Port gHashTag/trinity:fpga/openxc7-synth/d_bufg_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_bu #5781) + d_y0_test (Port gHashTag/trinity:fpga/openxc7-synth/d_y0_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_y0_t #5756);is_counter_power_of_twoin d_f19_test (Port gHashTag/trinity:fpga/openxc7-synth/d_f19_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_f19 #5797) + d_y0_test (Port gHashTag/trinity:fpga/openxc7-synth/d_y0_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_y0_t #5756);HirCoverPoint_validatein HirCoverPoint_new.t27 (Port bootstrap/src/compiler.rs lines 29486-29570 (Rust, 4 functions) to specs/port/bootstrap/src/compiler/HirCoverPoint_ #6192).python3 tools/dupe_scan.py --bless-- the diff is exactly +3 lines intools/duplicate_bodies_baseline.txt, andpython3 tools/dupe_scan.pynow printsok.3. Corpus ratchet (expected-failure ledger) -- fixed for the step that failed
tri types ratchet: ledger 77, observed 88 --BufgConfig CounterConfig CounterState Issue LedConfig LedOutputs ModuleInterface OscillatorState Outputs TbCheck TbConfigNEW.specs/port/trinity/fpga/openxc7-synth/(Port gHashTag/trinity:fpga/openxc7-synth/symbiflow_blink.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/ #5663, Port gHashTag/trinity:fpga/openxc7-synth/d_y0_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_y0_t #5756, Port gHashTag/trinity:fpga/openxc7-synth/d_g22_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_g22 #5757, Port gHashTag/trinity:fpga/openxc7-synth/d_bufg_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_bu #5781, Port gHashTag/trinity:fpga/openxc7-synth/led_both_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/le #5866, Port gHashTag/trinity:fpga/openxc7-synth/d_oscillator.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_o #5887, Port gHashTag/trinity:fpga/openxc7-synth/blink_minimal.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/bl #5956, Port gHashTag/trinity:fpga/openxc7-synth/led_diagnostic.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/l #6090, plus the earlier Port gHashTag/trinity:fpga/openxc7-synth/d_f19_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_f19 #5797/Port gHashTag/trinity:fpga/openxc7-synth/d_slow_blink.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_s #5798),specs/port/scripts/tri-search.t27(Port scripts/tri-search.py (Python, 1 function) to specs/port/scripts/tri-search.t27 #6191) andspecs/port/bootstrap/src/compiler/TbCheck_new.t27(Port bootstrap/src/compiler.rs lines 30386-30457 (Rust, 5 functions) to specs/port/bootstrap/src/compiler/TbCheck_new.t2 #6197).docs/reports/type_conflicts.jsonin exactly the shapetri types ratchet --blesswrites (serde pretty JSON, sorted). The next step of the same job,tri types classified, would otherwise have failed with 11 UNJUDGED names, so each was read and classified indocs/reports/type_conflicts_classified.jsonanddocs/TYPE_CONFLICTS.md: 7 DRIFT (BufgConfig, CounterConfig, CounterState, Issue, LedConfig, TbCheck, TbConfig), 4 DISTINCT (per-module port/state bundles: LedOutputs, ModuleInterface, OscillatorState, Outputs). Totals now 51 DRIFT / 37 DISTINCT = 88.t27c suite --ratchet --corpus-onlyran for the first time since the batch and reported 2 UNEXPECTED FAILURES atgen-verilog:specs/port/scripts/tri-issue-create.t27(Port scripts/tri-issue-create.py (Python, 1 function) to specs/port/scripts/tri-issue-create.t27 #5755) andspecs/port/trinity/src/vibeec/validation_engine.t27(Port gHashTag/trinity:src/vibeec/validation_engine.zig (Zig, 3 functions) to specs/port/trinity/src/vibeec/validation_en #5836). Both declare a local[N][]const u8string array, which the Verilog backend refuses (2-D array-of-aggregate lowering, W469). Recorded indocs/reports/suite_expectations.jsonunder Fifteen ported specs do not parse and need their ports redone #5549 with the other ports to be redone,expires2026-11-30;max_entries111 -> 113 by hand with the reason in_why_entries_rose.L1 TRACEABILITY (incidental)
Went red on the second push only because master moved: the check diffs
origin/master..HEADtwo-dot, so master's owngen/c/tri/t27b/steward.cchange (#6218) read as this PR's. Fixed by merging origin/master into the branch (merge commit, no force-push).4. coverage -- NOT fixed here
FAIL: 3 seal(s) newly do not hold--automation_automation::kanban_card_chat.json,runtime-process.json,runtime_runtime-process.jsonstale.specs/runtime/process.t27changed by 3d73d51 ("Add test for process_continue function", 11:02Z) after its seal at 10:29Z;specs/automation/kanban-card-chat.t27changed by 9a5b7f5 (kanban-card-chat v7).t27c seal <spec> --save && tri seals sync-twins, and the gen hashes it writes depend on the compiler. The only local t27c is from 2026-10-02 13:23, andbootstrap/srchas had ~30 codegen commits since; a seal from it would record hashes the current compiler does not produce. Per the owner rule, the rebuild belongs on the Railway lab / CI, not this Mac. Needs a reseal of those two specs with a t27c built from current master.🤖 Generated with Claude Code