fpga: elaboration ratchet back to 176 -- ternary_isa (W459), uart (spec), adapter (NEW-clean) (Closes #5908) by gHashTag · Pull Request #5948 · gHashTag/t27

gHashTag · 2026-10-04T07:44:45Z

Closes #5908
Part of #5906

FPGA Build / fpga-conformance failed at the elaboration ratchet with 178 (baseline 176). After this PR it prints 176 (baseline 176) OK and exits 0. This was reproduced exactly with master's t27c and iverilog 12.0.

(c) iverilog version: it moved no row

The baseline header said iverilog-version 13.0. CI does not pin iverilog: it runs apt-get install -y iverilog, which on ubuntu noble is 12.0-2build2.
The last green master run, 35677509145 on 6b15994, logged Unpacking iverilog (12.0-2build2) and 176 (baseline 176) OK. The 13.0-taken numbers therefore matched 12.0 row for row.
The baseline is now re-taken under 12.0 and its header says so. The total is unchanged at 176.

(a) Per row: cause, commit, proof

row	before -> after	cause	proof
`ternary_isa`	7 -> 6	`901ed4f` (#4594) added a test with a test-local `given stages = [...]`. W459 binds a `[N]T` parameter to the identifier at its call sites, test blocks included, and took that local for a module array. `pipeline_total_latency` lost `input [263:0] stages;` and indexed an undeclared name: `Unable to bind wire/reg/memory stages[...]`.	master t27c: `git show 901ed4fcc^:specs/fpga/ternary_isa.t27` -> 6 errors; `git show 901ed4fcc:specs/fpga/ternary_isa.t27` -> 7. The only Verilog diff is the lost `input` line.
`uart`	1 -> 0	`942a001` (#4651, whose message closed issue 2364) applied the issue's reproduction patch to the spec. It replaced `fn on_comb(data: u8) -> bool { return uart_tx_send(data); }` with an `on_clock` body: `uart.v:175: Could not find variable on_clock in ZeroDSP_UART`.	restoring the line gives 0 errors. Ports go back to `data`/`result`, which is what `contrib/formal/uart_formal_props.v` binds.
`adapter`	NEW -> recorded 0	`d4a7164` (S11 adapter contract) added `specs/fpga/adapter.t27`, which has 0 errors. The step still failed, because `if worse or new: return 1` counted a clean new module as a regression.	planted run: 178 = 178, only `NEW adapter 0`, exit 1.

Red runs on master: a90bdac (177, ternary_isa), 078f8ad (178, uart), then cadd11b (adds NEW adapter).

Fixes

bootstrap/src/compiler.rs (high-risk path, PR only). W459 now binds only when the identifier is a module-level const or var; anything else is passed by value (gen-verilog: packed-array param element index emits bit-select, not part-select #1745 part-selects). bootstrap/stage0/FROZEN_HASH is updated.
- Test first: bootstrap/tests/verilog_array_param_test_local.rs.
  - test_local_array_argument_is_passed_by_value checks for input [127:0] xs; and runs iverilog/vvp, expecting total = 10. It FAILED before the fix.
  - module_level_array_argument_is_still_bound is the W458 control: still bound, reads TABLE[i]. It passed before and after.
- verilog_array_param_index still passes.
specs/fpga/uart.t27. The on_comb line is restored. The gen-verilog: on_clock with a return type emits an assignment to an implicitly-declared identifier under default_nettype none #2364 compiler defect, an on_clock body assigning to an undeclared on_clock, is still live even though gen-verilog: on_clock with a return type emits an assignment to an implicitly-declared identifier under default_nettype none #2364 is closed. It is not fixed here.
tools/check_elab_ratchet.py. A new module with 0 errors is reported as NEW plus a "clean, record it with --update-baseline" line and exits 0. A new module with errors still fails. The self-check case NEW0 was written first and shown failing (exit = 1 (want 0)); --self-check now passes.
tools/elab_baseline.txt. Re-taken under iverilog 12.0. The only row added is adapter 0, with a note on why. ternary_isa and uart were not absorbed into the baseline: they were fixed.

Blast radius of the compiler fix

The Verilog of 10 specs changes; Zig, C and Rust output do not. iverilog error counts for those specs (only ternary_isa is in the ratchet set):

spec	before	after
compiler/lexer	71	21
tools/gft_generalize_demo	6	2
uuid	2	1
queen task_analysis	5	0
queen views	3	0
fpga/ternary_isa	7	6
prove, ternary_mac_demo_top, gen_kmeans	same	same
vsa/ops	13	14

vsa/ops is unmasking, not a regression. The old output bound one argument for all three array parameters and computed v+v+v. Now each is passed by value, and the remaining error is on lines that were already there.

Seals. The 15 seals whose Verilog hash moved are resealed with t27c seal --save. tools_GftGeneralizeDemo was resealed with --force: its softmax_picks_the_max_index test already fails with master's t27c (it was recorded blocked). tools/seal_baseline.txt gets a tests-fail row for it. UART_Bridge's seal records the restored uart spec. check_seal_currency.py and check_seal_coverage.py both exit 0.

The rest of fpga-conformance and the other FPGA jobs

On master run 37185428922 every fpga-conformance step after the ratchet was skipped, so none was red on its own. Locally on this branch they all pass:

fpga-conformance
- gate preconditions + self-check
- vector data + self-check
- mac 18 cases, spi 3 cases
- summary 34 CLEAN, schema 34 valid
fpga-lint
- yosys read_verilog -sv -DSIMULATION; hierarchy -top passes for 37/37 generated modules.
- t27c synth-readiness reports 38/38, READY FOR SYNTHESIS.
fpga-synthesis
- t27c fpga-build --docker false --synth-only completes under yosys 0.67, with and without --minimal. ZeroDSP_UART is synthesised inside ZeroDSP_TopLevel.

The other FPGA jobs (smoke, synthesis, synthesis-arty, formal, bitstream, report) were green on master. No hardware was touched or flashed.

Left open

gen-verilog: on_clock with a return type emits an assignment to an implicitly-declared identifier under default_nettype none #2364's compiler defect is still live; see above.
gft_generalize_demo's softmax_picks_the_max_index test is failing.
vsa/ops has errors that are now visible.
The comment at .github/workflows/fpga-build.yml:839 says the ratchet "has failed on every master run". It goes stale once this lands and is not edited here.

🤖 Generated with Claude Code

…plained (Closes #5908) Part of #5906. The FPGA Build / fpga-conformance ratchet printed 178 (baseline 176). iverilog version moved no row: CI installs 12.0 unpinned and master run 35677509145 printed 176 under 12.0. - ternary_isa 6 -> 7 (901ed4f, #4594): W459 bound an array parameter to a test-local `given stages = [...]`, deleting `input [263:0] stages;`. Compiler fix: bind only to a module-level const or var. Test first: bootstrap/tests/verilog_array_param_test_local.rs. FROZEN_HASH updated. - uart 0 -> 1 (942a001, #4651): the #2364 reproduction patch was applied to the spec. The on_comb line is restored. - adapter NEW 0 (d4a7164): a clean new module failed the step. check_elab_ratchet.py reports NEW-clean and exits 0. The self-check case NEW0 was written first and shown failing. adapter 0 recorded. The baseline was re-taken under iverilog 12.0, with the total unchanged at 176. Fifteen seals were resealed for the new Verilog hashes. GftGeneralizeDemo was resealed with --force because a test already fails on master; a tests-fail ledger row records it. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

…5908) The comment above "The gates in this file's table must fail loudly" said the elaboration ratchet "has failed on every master run". That stops being true once #5948 lands. It now says what the ratchet checks: each generated module's iverilog elaboration count is at most its row in tools/elab_baseline.txt, and a module new to the set passes only at 0. The a90bdac..#5908 failure is kept as history. Only comment lines change. The parsed workflow is identical at HEAD and after the edit (8 jobs, 42 run steps), so the cli-tri census does not move. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

github-actions · 2026-10-04T07:52:58Z

📓 NotebookLM Notebook linked to this PR

Notebook ID: b83263109fb055dc
URL: https://notebooklm.google.com/notebook/b83263109fb055dc

This notebook contains session context, decisions, and artifacts for this work.

github-actions · 2026-10-04T07:55:27Z

PR Dashboard

Generated at: 2026-10-04 07:55:18 UTC

Port gHashTag/trinity:fpga/openxc7-synth/blink_minimal.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/bl #5956 Port gHashTag/trinity:fpga/openxc7-synth/blink_minimal.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/bl | Created: 2026-10-04 | Updated: 2026-10-04 | 26 failing / 29 total
fix(gen-verilog): size struct and uN entry ports by one rule (#5904) #5955 fix(gen-verilog): size struct and uN entry ports by one rule (#5904) | Created: 2026-10-04 | Updated: 2026-10-04 | 30 failing / 33 total
docs(contributing): describe the docs/now entry the NOW gates check (#5950) #5952 docs(contributing): describe the docs/now entry the NOW gates check (#5950) | Created: 2026-10-04 | Updated: 2026-10-04 | 25 failing / 30 total
ci: remove the NOW gate -- nothing asks for a docs/now entry any more #5951 ci: remove the NOW gate -- nothing asks for a docs/now entry any more | Created: 2026-10-04 | Updated: 2026-10-04 | 21 failing / 31 total
fpga: elaboration ratchet back to 176 -- ternary_isa (W459), uart (spec), adapter (NEW-clean) (Closes #5908) #5948 fpga: elaboration ratchet back to 176 -- ternary_isa (W459), uart (spec), adapter (NEW-clean) (Closes #5908) | Created: 2026-10-04 | Updated: 2026-10-04 | 15 failing / 37 total
fix(t27c): refuse macro calls and typeless fields; rewrite eight Markdown specs (#5923) #5947 fix(t27c): refuse macro calls and typeless fields; rewrite eight Markdown specs (#5923) | Created: 2026-10-04 | Updated: 2026-10-04 | 11 failing / 40 total
Port gHashTag/trinity:src/background_agent/main.zig (Zig, 1 function) to specs/port/trinity/src/background_agent/main.t2 #5946 Port gHashTag/trinity:src/background_agent/main.zig (Zig, 1 function) to specs/port/trinity/src/background_agent/main.t2 | Created: 2026-10-04 | Updated: 2026-10-04 | 3 failing / 31 total
docs(contributing): document the fast t27c inner loop #5945 docs(contributing): document the fast t27c inner loop | Created: 2026-10-04 | Updated: 2026-10-04 | 0 failing / 30 total
spec(split-reel): v9 -- each voice is held to its own slowest measured pace #5932 spec(split-reel): v9 -- each voice is held to its own slowest measured pace | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 32 total
spec(automation/blog-share): v3 -- the owner's queue comes first; a switched-off network is not asked about #5931 spec(automation/blog-share): v3 -- the owner's queue comes first; a switched-off network is not asked about | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 34 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/provider-error-classifier.ts (TypeScript, 1 function) to #5926 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/provider-error-classifier.ts (TypeScript, 1 function) to | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 31 total
CI: spec-guards and emit-bitexact restore master cargo caches; cancel superseded emit-bitexact runs (B25) #5924 CI: spec-guards and emit-bitexact restore master cargo caches; cancel superseded emit-bitexact runs (B25) | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 32 total
ring-096 and formats.t27 agree on f32 (Closes #5746) #5921 ring-096 and formats.t27 agree on f32 (Closes #5746) | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 56 total
build(t27c): reqwest on native-tls, drop the aws-lc-sys build #5920 build(t27c): reqwest on native-tls, drop the aws-lc-sys build | Created: 2026-10-04 | Updated: 2026-10-04 | 5 failing / 37 total
build(t27c): put the web stack behind cargo features (212 -> 49 crates) #5914 build(t27c): put the web stack behind cargo features (212 -> 49 crates) | Created: 2026-10-04 | Updated: 2026-10-04 | 6 failing / 39 total
fix(rust): preserve writes to by-value parameter bindings #5911 [GOLD-RING] Infer writable Rust value parameter bindings | Created: 2026-10-04 | Updated: 2026-10-04 | 4 failing / 41 total
fix(t27c): var tuple destructure silences never-mutated Zig locals (Closes #5886) #5902 fix(t27c): var tuple destructure silences never-mutated Zig locals (Closes #5886) | Created: 2026-10-04 | Updated: 2026-10-04 | 3 failing / 46 total
chore(deps): drop unused candle-core/candle-nn from t27c (clean build 142.7 s -> 97.9 s) #5900 chore(deps): drop unused candle-core/candle-nn from t27c (clean build 142.7 s -> 97.9 s) | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 39 total
fix(tri tick): dirty work nobody holds is an anomaly, released claim or not #5896 fix(tri tick): dirty work nobody holds is an anomaly, released claim or not | Created: 2026-10-04 | Updated: 2026-10-04 | 3 failing / 34 total
fix(tri gates shell): a step whose run: key comes first is a step #5894 fix(tri gates shell): a step whose run: key comes first is a step | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 43 total
spec(crm-client-workspace): v6 -- client work carries the client's marks #5893 spec(crm-client-workspace): v6 -- client work carries the client's marks | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 34 total
Port gHashTag/trios:crates/trios-openclaw/rings/OC-01/src/lib.rs (Rust, 3 functions) to specs/port/trios/crates/trios-op #5888 Port gHashTag/trios:crates/trios-openclaw/rings/OC-01/src/lib.rs (Rust, 3 functions) to specs/port/trios/crates/trios-op | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 35 total
Port gHashTag/trinity:fpga/openxc7-synth/d_oscillator.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_o #5887 Port gHashTag/trinity:fpga/openxc7-synth/d_oscillator.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_o | Created: 2026-10-04 | Updated: 2026-10-04 | 5 failing / 35 total
Port scripts/test-agent-bridge.sh (Shell, 1 function) to specs/port/scripts/test-agent-bridge.t27 #5883 Port scripts/test-agent-bridge.sh (Shell, 1 function) to specs/port/scripts/test-agent-bridge.t27 | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 35 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/a2a/a2a-liveness.ts (TypeScript, 2 functions) to #5879 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/a2a/a2a-liveness.ts (TypeScript, 2 functions) to | Created: 2026-10-04 | Updated: 2026-10-04 | 3 failing / 35 total
feat(tri pr-state): --why, and each name under the heading tri printed it under #5868 feat(tri pr-state): --why, and each name under the heading tri printed it under | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 30 total
Port gHashTag/trinity:fpga/openxc7-synth/led_both_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/le #5866 Port gHashTag/trinity:fpga/openxc7-synth/led_both_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/le | Created: 2026-10-04 | Updated: 2026-10-04 | 4 failing / 35 total
fix(tri tick): a released claim is not held, and the dead-tick fix names its files #5864 fix(tri tick): a released claim is not held, and the dead-tick fix names its files | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 34 total
Port gHashTag/trios:crates/trios-scarab-types/rings/SR-01/src/lib.rs (Rust, 6 functions) to specs/port/trios/crates/trio #5855 Port gHashTag/trios:crates/trios-scarab-types/rings/SR-01/src/lib.rs (Rust, 6 functions) to specs/port/trios/crates/trio | Created: 2026-10-04 | Updated: 2026-10-04 | 4 failing / 35 total
feat(tri pr ready): --why compares what a pre-existing failure printed #5853 feat(tri pr ready): --why compares what a pre-existing failure printed | Created: 2026-10-04 | Updated: 2026-10-04 | 3 failing / 38 total
feat(tri): tri harness measures a page signed in -- --save-state / --storage-state, sessionStorage included #5849 feat(tri): tri harness measures a page signed in -- --save-state / --storage-state, sessionStorage included | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 35 total
feat(tri pr ready): ask a check's own workflow when the commit window missed it #5839 feat(tri pr ready): ask a check's own workflow when the commit window missed it | Created: 2026-10-03 | Updated: 2026-10-03 | 3 failing / 41 total
Port gHashTag/trinity:src/vibeec/validation_engine.zig (Zig, 3 functions) to specs/port/trinity/src/vibeec/validation_en #5836 Port gHashTag/trinity:src/vibeec/validation_engine.zig (Zig, 3 functions) to specs/port/trinity/src/vibeec/validation_en | Created: 2026-10-03 | Updated: 2026-10-04 | 5 failing / 35 total
feat(tri): tri harness -- a page measured at 375px and 1024px, every visible frame #5828 feat(tri): tri harness -- a page measured at 375px and 1024px, every visible frame | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 37 total
feat(tri census explain): name the file behind a moved census number #5826 feat(tri census explain): name the file behind a moved census number | Created: 2026-10-03 | Updated: 2026-10-03 | 3 failing / 39 total
tri pr-state: a loop's pull requests with tri pr ready's verdict, not "open" #5824 tri pr-state: a loop's pull requests with tri pr ready's verdict, not "open" | Created: 2026-10-03 | Updated: 2026-10-03 | 1 failing / 32 total
Port gHashTag/trinity:fpga/openxc7-synth/blink_simple.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/bli #5822 Port gHashTag/trinity:fpga/openxc7-synth/blink_simple.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/bli | Created: 2026-10-03 | Updated: 2026-10-04 | 4 failing / 35 total
Port gHashTag/trinity:fpga/openxc7-synth/uart_echo.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/uart_e #5820 Port gHashTag/trinity:fpga/openxc7-synth/uart_echo.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/uart_e | Created: 2026-10-03 | Updated: 2026-10-04 | 4 failing / 35 total
tri: stranded-work finder and cron tick resume card #5787 tri: stranded-work finder and cron tick resume card | Created: 2026-10-03 | Updated: 2026-10-03 | 1 failing / 31 total
Port gHashTag/trinity:fpga/openxc7-synth/d_srl_blink.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_sr #5783 Port gHashTag/trinity:fpga/openxc7-synth/d_srl_blink.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_sr | Created: 2026-10-03 | Updated: 2026-10-04 | 2 failing / 36 total
Port gHashTag/trinity:fpga/openxc7-synth/d_bufg_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_bu #5781 Port gHashTag/trinity:fpga/openxc7-synth/d_bufg_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_bu | Created: 2026-10-03 | Updated: 2026-10-04 | 3 failing / 36 total
Port gHashTag/trinity:fpga/openxc7-synth/led_on_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/led_ #5780 Port gHashTag/trinity:fpga/openxc7-synth/led_on_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/led_ | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 36 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/queen-lane-credits.ts (TypeScript, 4 functions) #5778 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/queen-lane-credits.ts (TypeScript, 4 functions) | Created: 2026-10-03 | Updated: 2026-10-03 | 3 failing / 32 total
bees/merger/publisher: reviewer bee as a service, merger reads discounted checks, publisher heading passes check (Closes #5776) #5777 bees/merger/publisher: reviewer bee as a service, merger reads discounted checks, publisher heading passes check (Closes #5776) | Created: 2026-10-03 | Updated: 2026-10-04 | 0 failing / 31 total
Port gHashTag/trinity:fpga/openxc7-synth/d_g22_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_g22 #5757 Port gHashTag/trinity:fpga/openxc7-synth/d_g22_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_g22 | Created: 2026-10-03 | Updated: 2026-10-03 | 3 failing / 35 total
Port gHashTag/trinity:fpga/openxc7-synth/d_y0_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_y0_t #5756 Port gHashTag/trinity:fpga/openxc7-synth/d_y0_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_y0_t | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 37 total
Port scripts/tri-issue-create.py (Python, 1 function) to specs/port/scripts/tri-issue-create.t27 #5755 Port scripts/tri-issue-create.py (Python, 1 function) to specs/port/scripts/tri-issue-create.t27 | Created: 2026-10-03 | Updated: 2026-10-03 | 3 failing / 37 total
fix(tri): gates preview reads the PR body the way the issue gate does (Closes #5744) #5745 fix(tri): gates preview reads the PR body the way the issue gate does (Closes #5744) | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 42 total
fix(tri): gates preview asks the contexts the ruleset requires, parse-ratchet among them (Closes #5725) #5732 fix(tri): gates preview asks the contexts the ruleset requires, parse-ratchet among them (Closes #5725) | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 43 total
Port gHashTag/trinity:fpga/openxc7-synth/d_e21_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_e21 #5689 Port gHashTag/trinity:fpga/openxc7-synth/d_e21_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_e21 | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 32 total

Summary

Status	Count
Total Open PRs	50
PRs with Failing Checks	43
PRs with All Checks Green	7
READY	2
FAILING	43
PENDING	0
NO CHECKS YET	0

These columns do not partition: 2 + 43 + 0 + 0 = 45, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

⚠️ STALE -- sha256(compiler.rs)=aad9a8fd3343 != manifest seal=87e5cbd3ad94.
The committed NMSE numbers were certified against an older compiler.rs.
Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

github-actions · 2026-10-04T07:57:27Z

PR Dashboard

Generated at: 2026-10-04 07:57:16 UTC

Port gHashTag/trinity:fpga/openxc7-synth/blink_minimal.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/bl #5956 Port gHashTag/trinity:fpga/openxc7-synth/blink_minimal.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/bl | Created: 2026-10-04 | Updated: 2026-10-04 | 26 failing / 29 total
fix(gen-verilog): size struct and uN entry ports by one rule (#5904) #5955 fix(gen-verilog): size struct and uN entry ports by one rule (#5904) | Created: 2026-10-04 | Updated: 2026-10-04 | 27 failing / 33 total
docs(contributing): describe the docs/now entry the NOW gates check (#5950) #5952 docs(contributing): describe the docs/now entry the NOW gates check (#5950) | Created: 2026-10-04 | Updated: 2026-10-04 | 17 failing / 31 total
ci: remove the NOW gate -- nothing asks for a docs/now entry any more #5951 ci: remove the NOW gate -- nothing asks for a docs/now entry any more | Created: 2026-10-04 | Updated: 2026-10-04 | 18 failing / 31 total
fpga: elaboration ratchet back to 176 -- ternary_isa (W459), uart (spec), adapter (NEW-clean) (Closes #5908) #5948 fpga: elaboration ratchet back to 176 -- ternary_isa (W459), uart (spec), adapter (NEW-clean) (Closes #5908) | Created: 2026-10-04 | Updated: 2026-10-04 | 15 failing / 37 total
fix(t27c): refuse macro calls and typeless fields; rewrite eight Markdown specs (#5923) #5947 fix(t27c): refuse macro calls and typeless fields; rewrite eight Markdown specs (#5923) | Created: 2026-10-04 | Updated: 2026-10-04 | 10 failing / 40 total
Port gHashTag/trinity:src/background_agent/main.zig (Zig, 1 function) to specs/port/trinity/src/background_agent/main.t2 #5946 Port gHashTag/trinity:src/background_agent/main.zig (Zig, 1 function) to specs/port/trinity/src/background_agent/main.t2 | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 31 total
docs(contributing): document the fast t27c inner loop #5945 docs(contributing): document the fast t27c inner loop | Created: 2026-10-04 | Updated: 2026-10-04 | 0 failing / 30 total
spec(split-reel): v9 -- each voice is held to its own slowest measured pace #5932 spec(split-reel): v9 -- each voice is held to its own slowest measured pace | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 32 total
spec(automation/blog-share): v3 -- the owner's queue comes first; a switched-off network is not asked about #5931 spec(automation/blog-share): v3 -- the owner's queue comes first; a switched-off network is not asked about | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 34 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/provider-error-classifier.ts (TypeScript, 1 function) to #5926 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/provider-error-classifier.ts (TypeScript, 1 function) to | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 31 total
CI: spec-guards and emit-bitexact restore master cargo caches; cancel superseded emit-bitexact runs (B25) #5924 CI: spec-guards and emit-bitexact restore master cargo caches; cancel superseded emit-bitexact runs (B25) | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 32 total
ring-096 and formats.t27 agree on f32 (Closes #5746) #5921 ring-096 and formats.t27 agree on f32 (Closes #5746) | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 56 total
build(t27c): reqwest on native-tls, drop the aws-lc-sys build #5920 build(t27c): reqwest on native-tls, drop the aws-lc-sys build | Created: 2026-10-04 | Updated: 2026-10-04 | 4 failing / 37 total
build(t27c): put the web stack behind cargo features (212 -> 49 crates) #5914 build(t27c): put the web stack behind cargo features (212 -> 49 crates) | Created: 2026-10-04 | Updated: 2026-10-04 | 5 failing / 39 total
fix(rust): preserve writes to by-value parameter bindings #5911 fix(rust): preserve writes to by-value parameter bindings | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 2 total
fix(t27c): var tuple destructure silences never-mutated Zig locals (Closes #5886) #5902 fix(t27c): var tuple destructure silences never-mutated Zig locals (Closes #5886) | Created: 2026-10-04 | Updated: 2026-10-04 | 3 failing / 46 total
chore(deps): drop unused candle-core/candle-nn from t27c (clean build 142.7 s -> 97.9 s) #5900 chore(deps): drop unused candle-core/candle-nn from t27c (clean build 142.7 s -> 97.9 s) | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 39 total
fix(tri tick): dirty work nobody holds is an anomaly, released claim or not #5896 fix(tri tick): dirty work nobody holds is an anomaly, released claim or not | Created: 2026-10-04 | Updated: 2026-10-04 | 3 failing / 34 total
fix(tri gates shell): a step whose run: key comes first is a step #5894 fix(tri gates shell): a step whose run: key comes first is a step | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 43 total
spec(crm-client-workspace): v6 -- client work carries the client's marks #5893 spec(crm-client-workspace): v6 -- client work carries the client's marks | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 34 total
Port gHashTag/trios:crates/trios-openclaw/rings/OC-01/src/lib.rs (Rust, 3 functions) to specs/port/trios/crates/trios-op #5888 Port gHashTag/trios:crates/trios-openclaw/rings/OC-01/src/lib.rs (Rust, 3 functions) to specs/port/trios/crates/trios-op | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 35 total
Port gHashTag/trinity:fpga/openxc7-synth/d_oscillator.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_o #5887 Port gHashTag/trinity:fpga/openxc7-synth/d_oscillator.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_o | Created: 2026-10-04 | Updated: 2026-10-04 | 5 failing / 35 total
Port scripts/test-agent-bridge.sh (Shell, 1 function) to specs/port/scripts/test-agent-bridge.t27 #5883 Port scripts/test-agent-bridge.sh (Shell, 1 function) to specs/port/scripts/test-agent-bridge.t27 | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 35 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/a2a/a2a-liveness.ts (TypeScript, 2 functions) to #5879 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/a2a/a2a-liveness.ts (TypeScript, 2 functions) to | Created: 2026-10-04 | Updated: 2026-10-04 | 3 failing / 35 total
feat(tri pr-state): --why, and each name under the heading tri printed it under #5868 feat(tri pr-state): --why, and each name under the heading tri printed it under | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 30 total
Port gHashTag/trinity:fpga/openxc7-synth/led_both_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/le #5866 Port gHashTag/trinity:fpga/openxc7-synth/led_both_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/le | Created: 2026-10-04 | Updated: 2026-10-04 | 4 failing / 35 total
fix(tri tick): a released claim is not held, and the dead-tick fix names its files #5864 fix(tri tick): a released claim is not held, and the dead-tick fix names its files | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 34 total
Port gHashTag/trios:crates/trios-scarab-types/rings/SR-01/src/lib.rs (Rust, 6 functions) to specs/port/trios/crates/trio #5855 Port gHashTag/trios:crates/trios-scarab-types/rings/SR-01/src/lib.rs (Rust, 6 functions) to specs/port/trios/crates/trio | Created: 2026-10-04 | Updated: 2026-10-04 | 4 failing / 35 total
feat(tri pr ready): --why compares what a pre-existing failure printed #5853 feat(tri pr ready): --why compares what a pre-existing failure printed | Created: 2026-10-04 | Updated: 2026-10-04 | 3 failing / 38 total
feat(tri): tri harness measures a page signed in -- --save-state / --storage-state, sessionStorage included #5849 feat(tri): tri harness measures a page signed in -- --save-state / --storage-state, sessionStorage included | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 35 total
feat(tri pr ready): ask a check's own workflow when the commit window missed it #5839 feat(tri pr ready): ask a check's own workflow when the commit window missed it | Created: 2026-10-03 | Updated: 2026-10-03 | 3 failing / 41 total
Port gHashTag/trinity:src/vibeec/validation_engine.zig (Zig, 3 functions) to specs/port/trinity/src/vibeec/validation_en #5836 Port gHashTag/trinity:src/vibeec/validation_engine.zig (Zig, 3 functions) to specs/port/trinity/src/vibeec/validation_en | Created: 2026-10-03 | Updated: 2026-10-04 | 5 failing / 35 total
feat(tri): tri harness -- a page measured at 375px and 1024px, every visible frame #5828 feat(tri): tri harness -- a page measured at 375px and 1024px, every visible frame | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 37 total
feat(tri census explain): name the file behind a moved census number #5826 feat(tri census explain): name the file behind a moved census number | Created: 2026-10-03 | Updated: 2026-10-03 | 3 failing / 39 total
tri pr-state: a loop's pull requests with tri pr ready's verdict, not "open" #5824 tri pr-state: a loop's pull requests with tri pr ready's verdict, not "open" | Created: 2026-10-03 | Updated: 2026-10-03 | 1 failing / 32 total
Port gHashTag/trinity:fpga/openxc7-synth/blink_simple.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/bli #5822 Port gHashTag/trinity:fpga/openxc7-synth/blink_simple.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/bli | Created: 2026-10-03 | Updated: 2026-10-04 | 4 failing / 35 total
Port gHashTag/trinity:fpga/openxc7-synth/uart_echo.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/uart_e #5820 Port gHashTag/trinity:fpga/openxc7-synth/uart_echo.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/uart_e | Created: 2026-10-03 | Updated: 2026-10-04 | 4 failing / 35 total
tri: stranded-work finder and cron tick resume card #5787 tri: stranded-work finder and cron tick resume card | Created: 2026-10-03 | Updated: 2026-10-03 | 1 failing / 31 total
Port gHashTag/trinity:fpga/openxc7-synth/d_srl_blink.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_sr #5783 Port gHashTag/trinity:fpga/openxc7-synth/d_srl_blink.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_sr | Created: 2026-10-03 | Updated: 2026-10-04 | 2 failing / 36 total
Port gHashTag/trinity:fpga/openxc7-synth/d_bufg_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_bu #5781 Port gHashTag/trinity:fpga/openxc7-synth/d_bufg_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_bu | Created: 2026-10-03 | Updated: 2026-10-04 | 3 failing / 36 total
Port gHashTag/trinity:fpga/openxc7-synth/led_on_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/led_ #5780 Port gHashTag/trinity:fpga/openxc7-synth/led_on_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/led_ | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 36 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/queen-lane-credits.ts (TypeScript, 4 functions) #5778 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/queen-lane-credits.ts (TypeScript, 4 functions) | Created: 2026-10-03 | Updated: 2026-10-03 | 3 failing / 32 total
bees/merger/publisher: reviewer bee as a service, merger reads discounted checks, publisher heading passes check (Closes #5776) #5777 bees/merger/publisher: reviewer bee as a service, merger reads discounted checks, publisher heading passes check (Closes #5776) | Created: 2026-10-03 | Updated: 2026-10-04 | 0 failing / 31 total
Port gHashTag/trinity:fpga/openxc7-synth/d_g22_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_g22 #5757 Port gHashTag/trinity:fpga/openxc7-synth/d_g22_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_g22 | Created: 2026-10-03 | Updated: 2026-10-03 | 3 failing / 35 total
Port gHashTag/trinity:fpga/openxc7-synth/d_y0_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_y0_t #5756 Port gHashTag/trinity:fpga/openxc7-synth/d_y0_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_y0_t | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 37 total
Port scripts/tri-issue-create.py (Python, 1 function) to specs/port/scripts/tri-issue-create.t27 #5755 Port scripts/tri-issue-create.py (Python, 1 function) to specs/port/scripts/tri-issue-create.t27 | Created: 2026-10-03 | Updated: 2026-10-03 | 3 failing / 37 total
fix(tri): gates preview reads the PR body the way the issue gate does (Closes #5744) #5745 fix(tri): gates preview reads the PR body the way the issue gate does (Closes #5744) | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 42 total
fix(tri): gates preview asks the contexts the ruleset requires, parse-ratchet among them (Closes #5725) #5732 fix(tri): gates preview asks the contexts the ruleset requires, parse-ratchet among them (Closes #5725) | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 43 total
Port gHashTag/trinity:fpga/openxc7-synth/d_e21_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_e21 #5689 Port gHashTag/trinity:fpga/openxc7-synth/d_e21_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_e21 | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 32 total

Summary

Status	Count
Total Open PRs	50
PRs with Failing Checks	42
PRs with All Checks Green	8
READY	2
FAILING	42
PENDING	0
NO CHECKS YET	0

These columns do not partition: 2 + 42 + 0 + 0 = 44, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

⚠️ STALE -- sha256(compiler.rs)=aad9a8fd3343 != manifest seal=87e5cbd3ad94.
The committed NMSE numbers were certified against an older compiler.rs.
Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

gHashTag · 2026-10-06T07:04:23Z

PR #6686 takes this PR's t27 and data parts (the uart on_comb line, adapter 0, the iverilog 12.0 header) so master's fpga-conformance can go green, and records ternary_isa 7 as a known gap (#6685). The compiler, ratchet-script and workflow changes here are hand-written Rust/Python/yml and need the owner's owner-approved-foreign label under the only-t27 rule. Once labelled and merged, this PR should bring ternary_isa back to 6 and drop its baseline row to match; it will also need Closes #6685 instead of #5908.

This was referenced Oct 4, 2026

gen-verilog: on_clock with a return type emits an assignment to an implicitly-declared identifier under default_nettype none #2364

Open

EPIC: master's three inherited reds and the review-speed follow-ups (2026-10-04) #5906

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github-actions Bot mentioned this pull request Oct 4, 2026

Port gHashTag/trinity:src/background_agent/main.zig (Zig, 1 function) to specs/port/trinity/src/background_agent/main.t2 #5946

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github-actions Bot mentioned this pull request Oct 4, 2026

ci: remove the NOW gate -- nothing asks for a docs/now entry any more #5951

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gHashTag mentioned this pull request Oct 6, 2026

gen-verilog W459 binds a test-local array to a module array: ternary_isa 6 -> 7 elaboration errors #6685

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github-actions Bot mentioned this pull request Oct 6, 2026

fix(proofs): real Lean model for ar_ternary_logic, theorem = false; leave the ledger #6684

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gHashTag mentioned this pull request Oct 6, 2026

fix(fpga): elaboration ratchet green -- uart restored, adapter recorded, ternary_isa a named gap #6686

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fpga: elaboration ratchet back to 176 -- ternary_isa (W459), uart (spec), adapter (NEW-clean) (Closes #5908) - #5948

fpga: elaboration ratchet back to 176 -- ternary_isa (W459), uart (spec), adapter (NEW-clean) (Closes #5908)#5948
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gHashTag commented Oct 4, 2026 •

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(c) iverilog version: it moved no row

(a) Per row: cause, commit, proof

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gHashTag commented Oct 4, 2026 •

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