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Port fpga/verilog/mvp_ternary_classifier_check.v (Verilog, 1 module) to specs/port/fpga/verilog/mvp_ternary_classifier_c - #6853

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queen-5074
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gHashTag wants to merge 2 commits into
masterfrom
queen-5074

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@gHashTag gHashTag commented Oct 6, 2026

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Closes #5074

Written by a bee on queen-5074 and published by tools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.

1 file changed, 223 insertions(+)

🤖 Generated with Claude Code

Trinity Bee and others added 2 commits October 5, 2026 22:25
…erilog/mvp_ternary_classifier_check.t27

- Port the decision logic from the original Verilog module
- Include reference values for 10 test cases from the spec header
- Implement range checking (output must be 0, 1, or 2)
- Add comprehensive tests for all decision logic
- Maintain the same module name and parameter

Closes #5074
A pull request must add exactly one docs/now entry and a bee has no way
to know that: its brief names a boundary file and acceptance criteria,
and docs/now/ is neither. The publisher adds it rather than failing the
gate.

Closes #5074

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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PR Dashboard

Generated at: 2026-10-06 13:55:04 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 40
PRs with All Checks Green 10
READY 0
FAILING 40
PENDING 0
NO CHECKS YET 0

These columns do not partition: 0 + 40 + 0 + 0 = 40, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=3c78f3c7ffb7 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

This was referenced Oct 6, 2026
This was referenced Oct 6, 2026

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Port fpga/verilog/mvp_ternary_classifier_check.v (Verilog, 1 module) to specs/port/fpga/verilog/mvp_ternary_classifier_check.t27

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