Skip to content

Port fpga/verilog/mvp_ternary_classifier_top.v (Verilog, 1 module) to specs/port/fpga/verilog/mvp_ternary_classifier_top - #6882

Merged
gHashTag merged 2 commits into
masterfrom
queen-5030
Oct 7, 2026
Merged

gHashTag merged 2 commits into
masterfrom
queen-5030

Conversation

@gHashTag

@gHashTag gHashTag commented Oct 6, 2026

Copy link
Copy Markdown
Owner

Closes #5030

Written by a bee on queen-5030 and published by tools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.

1 file changed, 192 insertions(+)

🤖 Generated with Claude Code

Trinity Bee and others added 2 commits October 5, 2026 18:04
…ilog/mvp_ternary_classifier_top.t27

Re-author the hand-written Verilog as a .t27 module so the code is generated
from .t27 instead of written by hand. The module describes the same functionality
as the original, with tests for the LED status interpretation and clock configuration.

Closes #5030
A pull request must add exactly one docs/now entry and a bee has no way
to know that: its brief names a boundary file and acceptance criteria,
and docs/now/ is neither. The publisher adds it rather than failing the
gate.

Closes #5030

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
@github-actions

github-actions Bot commented Oct 6, 2026

Copy link
Copy Markdown
Contributor

PR Dashboard

Generated at: 2026-10-06 14:38:20 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 40
PRs with All Checks Green 10
READY 1
FAILING 40
PENDING 0
NO CHECKS YET 0

These columns do not partition: 1 + 40 + 0 + 0 = 41, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=0ec05a8c1a46 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

This was referenced Oct 6, 2026
This was referenced Oct 6, 2026
@gHashTag
gHashTag enabled auto-merge (squash) October 7, 2026 07:25
@gHashTag
gHashTag merged commit bcabc8b into master Oct 7, 2026
21 of 26 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

Port fpga/verilog/mvp_ternary_classifier_top.v (Verilog, 1 module) to specs/port/fpga/verilog/mvp_ternary_classifier_top.t27

2 participants