gen-verilog: an entry parameter named clk/rst_n/en is declared once; a void body's last call stays a statement (Closes #5649, Closes #5650, Closes #5651)

[dmitrii-f-t27]

Closes #5649
Closes #5650
Closes #5651

Description

Three t27c gen-verilog defects that made iverilog refuse generated modules.

• gen-verilog: an entry-point parameter named clk/rst_n/en is declared twice in the module header #5649 An on_comb / on_clock parameter named like a header port (clk, rst_n, en) was declared a second time. Five corpus specs: d_bank13_test, d_direct, led_simple_test, led_test_inv (fn on_comb(clk: bool)), dsp_probe (fn on_clock(cfgmclk: bool, rst_n: bool, en: bool)).
• gen-verilog: the tail-expression rule turns the last call in a void fn or on_clock into an assignment to the fn's own name #5651 The tail-expression rule (t27#1948) lowered the last call of a body that returns nothing to <fn> = <expr>;: fn reset() { ...; tick(); } became reset = tick(1'b0); inside task reset, and a void on_clock became on_clock <= f(d);. The predicate tested only the spelling "void", and gen_verilog_clocked_fn never set the return type it was judged by.
• gen-verilog: zero-argument on_comb is driven as assign result = on_comb(); without the W530 placeholder argument #5650 (assign result = on_comb();) was already fixed on master by fix(gen-verilog): size struct and uN entry ports by one rule (#5904) #5955 (for gen-verilog refuses an on_comb over a struct or u1 although its own functions lower both -- ternary_mac stays at 0 cells #5904). This PR adds the regression pin the issue asks for.

Spec

The decisions live in .t27, lowered by t27c gen-rust to bootstrap/gen/rust/compiler/ and mounted by #[path] (the verilog_aos_memory.t27 pattern, #8151):

• specs/compiler/verilog_entry_port_collision.t27 (7 tests): a 1-bit unsigned parameter IS the header port and is declared once; a wider or signed one refuses the entry point (W699 path, file and stderr), never narrowed; a non-colliding parameter keeps its own port.
• specs/compiler/verilog_void_tail.t27 (4 tests): only a function whose return type is written and is not void gets the implicit return. Both tail sites (bare tail, final if/else) read it; on_clock sets its own return type and clears it on exit.
• specs/compiler/verilog_on_comb_zero_arg.t27 (1 test): a fixture with fn on_comb() -> bool; its seal pins assign result = on_comb(1'b0);. The two corpus specs of gen-verilog: zero-argument on_comb is driven as assign result = on_comb(); without the W530 placeholder argument #5650 cannot be sealed: their module name trinity_top already owns the seal file in that directory (seal store: two specs derive one seal file name, and seal --save overwrites the other spec's seal #8540).

Only t27 (owner rules 2026-10-05 and 2026-10-09)

The issues asked for new bootstrap/tests/*.rs regression tests. A new hand-written .rs file is now denied, so the regression guards are the three specs and the resealed gen_hash_verilog of every sealed spec whose output changed (the suite's seal-verify phase reports any drift). compiler.rs is +25/-11 and FROZEN_HASH 1/1; paid for by deleting scripts/gen_w369.py (a one-shot wave-369 generator nothing runs, as #8617 and #8667 did with gen_w378.py / gen_w379.py). Local own_language.c check_all and check_budget: both 0.

Measured (master tip vs this branch, merged with master d01d772)

• Whole corpus, gen-verilog with a master-tip t27c and with this tree's t27c: 51 of 2230 .t27 files change. 5 lose exactly the duplicated header line(s) (gen-verilog: an entry-point parameter named clk/rst_n/en is declared twice in the module header #5649); 46 change 88 lines, each exactly <name> = <expr>; -> <expr>; (gen-verilog: the tail-expression rule turns the last call in a void fn or on_clock into an assignment to the fn's own name #5651). Nothing else changes; exit codes and stderr are identical.
• iverilog -g2012: the 5 gen-verilog: an entry-point parameter named clk/rst_n/en is declared twice in the module header #5649 specs fail before and pass after; of the 46 gen-verilog: the tail-expression rule turns the last call in a void fn or on_clock into an assignment to the fn's own name #5651 files, 0 passed before and 23 pass after (the 22 specs/fpga/testbench/*_tb.t27 and specs/tri/t27b/conformance/value_ignored.t27). No file regresses.
• Success Criteria, this tree's t27c: gen-verilog: an entry-point parameter named clk/rst_n/en is declared twice in the module header #5649 all 10 hold (clk declared 1 time in d_bank13_test / led_simple_test / led_test_inv, rst_n|en 2 and duplicates 0 in dsp_probe, cfgmclk 1, assign result = on_comb(clk); 1, ternary_node 8 inputs, 0 duplicates). gen-verilog: the tail-expression rule turns the last call in a void fn or on_clock into an assignment to the fn's own name #5651: reset = tick 0 in bridge_tb, dft_tb, memory_tb, spi_tb, apb_bridge_tb; reset = tick_slow 0 in clock_domain_tb; bridge_tb tick(1'b0); 7, task reset; 1; ternary_mac_synth product = __mul_noop( 1. The two specs/fpga/uart.t27 criteria no longer apply: fix(fpga): elaboration ratchet green -- uart restored, adapter recorded, ternary_isa a named gap #6686 replaced its on_clock with on_comb; a void on_clock ending in a call was checked with a scratch spec instead (on_clock <= 1 -> 0, iverilog fails -> passes). gen-verilog: zero-argument on_comb is driven as assign result = on_comb(); without the W530 placeholder argument #5650: d_full_path / d_static_one on_comb() 0, on_comb(1'b0) 1, input _unused; 1, ternary_node unchanged.
• Seals: 44 sealed specs change Verilog output; all 44 verify MATCH with the master-tip t27c before, and are resealed with this tree's t27c (only gen_hash_verilog changes; forced seals keep the same failing tests). 3 new specs sealed.
• t27c test-report: the three specs 7/7, 4/4, 1/1 pass, 0 vacuous (zig 0.16.0).
• cargo test -p t27c for verilog_struct_entry_ports, verilog_branch_context, on_clock_plain_assign, clocked_counter, duplicate_declarations, behavior_sva_v2: all pass. The 16 scenario tests first written as bootstrap/tests/*.rs also pass locally; they are not committed (Only t27).
• t27b_expectations.json: verilog_entry_port_collision.t27 listed as pass, as this PR's t27b ratchet measured it (run 38092422487: "the reference passes it ... (t27b pass)"). verilog_void_tail.t27 and verilog_on_comb_zero_arg.t27 likewise, from run 38094798157 on aca8a31.

Limits

• A parameter named like a header port in a spec that also declares a module var of that name is not judged here (no corpus spec has one).
• A return <expr>; written in a void fn (e.g. return undefined;) still becomes <fn> = <expr>;: that is the explicit-return path, not the tail rule, and is out of scope (17 files on master).
• Red checks that are red on master too are listed in a comment with links.

Dmitrii Fedorov (@dmitrii-f-t27)

[dmitrii-f-t27]

Updated 2026-10-11 for head f042d0009 (the PR was in conflict with master; resolved by a merge commit, no rebase, no force-push).

What changed since ba9cba6a0

• dcf9c6f04 merges master 5e5493cab. bootstrap/src/compiler.rs keeps both #[path] blocks (master's cse_hoist/int_type_names and this PR's two modules); FROZEN_HASH is the sha256 of the merged file; the t27b ledger keeps master's zig_empty_typed_array = pass.
• 4ec4f3ec3 reseals. Every seal file first took master's version. Then t27c seal --verify ran over all 2416 seals twice: with a master-tip t27c on master, and with this tree's t27c (built from dcf9c6f04). The only difference is 44 specs (73 seal files) whose gen_hash_verilog moves; only those are resealed. Forced seals keep the same failing tests and pass/total counts. After the reseal, the non-MATCH set equals master's exactly (queen/holds.t27 rust drift, sandbox.tri vacuous, three docs without seals, 53 seals whose spec is gone).
• f042d0009 deletes scripts/gen_w389.py (54 lines; its decision is ported in specs/port/scripts/gen_w389.t27). Master already deleted gen_w369.py in frontier --watch reruns a batch side by side, specs sharing a file stem on one worker -- 16 reruns 34.5 s -> 13.9 s (Closes #8852) #8856, so the earlier offset for compiler.rs's +14 hand-written lines was gone and own-language went red on 4ec4f3ec3; this restores it (same precedent as gen-zig: a local declared []T from an array literal lowers to @constCast(&[_]T{...}) (Closes #8602) #8617 and frontier --watch reruns a batch side by side, specs sharing a file stem on one worker -- 16 reruns 34.5 s -> 13.9 s (Closes #8852) #8856).

Local checks with this tree's t27c: test-report on the three specs: 7/7, 4/4, 1/1, 0 vacuous; gen-rust output is byte-identical to the two committed files; cargo test --release for verilog_struct_entry_ports 9, verilog_branch_context 6, on_clock_plain_assign 2, clocked_counter 1, duplicate_declarations 13, behavior_sva_v2 32: all ok.

CI on head f042d0009: 35 green, 7 red. The four required checks pass (validate, check-linked-issue, parse-ratchet, own-language). Each red check gives the same findings on master:

check	this PR	master
spec-guards	run: 1 stale, queen_QueenHolds.json gen_hash_rust	5e5493cab: the same
coverage	run: queen_QueenHolds.json gen-drift	5e5493cab: the same
Corpus ratchet	run: types ledger 86 vs 89, NEW Entry, Inputs, SkillMeta	5e5493cab: the same
t27b-native-ratchet	run: 17 UNLISTED, none of them this PR's	5e5493cab: the same 17
cli-tri	run: census quiet 185 -> 188, shell 305 -> 306	a31427373 push: the same numbers; this PR does not touch .github/ or cli/
fpga-lint	run: 3/54 modules	9b4338a67 push: 3/54 modules
fpga-conformance	run: 206 vs baseline 205, NEW die_probe, eth_reply, eye_isi, line_bounce, ro_race	9b4338a67 push: the same

emit-bitexact, duplicate-bodies and Verilog widths, red on the old head, are green now.

Status: mergeable at f042d0009, required checks green. If master moves into conflict again, I will merge master again and reseal with this tree's t27c.

Dmitrii Fedorov (@dmitrii-f-t27)