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Port gHashTag/trinity:fpga/openxc7-synth/gf16_adder.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/gf16_ - #8901
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Faithful t27 port of the upstream Verilog module fpga/openxc7-synth/gf16_adder.v (local source: fpga/vivado/gf16_add.v): a 16-bit float adder with bias-31 exponent, NaN/Inf/zero special-case handling, 7-bit barrel-shift alignment, 12-bit significand sum with opposite-sign cancellation, msb-scan normalization ladder, and overflow/underflow clamps to signed zero and infinity. - on_comb(a, b) -> u16 data port; helpers kept private (exp_of, mant_of, sign_of, is_special, is_inf, is_nan, is_zero, low_msb, norm_down) - special-case priority, zero passthrough, and clamp semantics transcribed with origin-line comments; r_bit/s_bit rounding and the rounded<norm carry correction are provably dead in the original (both sticky bits are hardwired 0) and are documented as omitted - sum_m[11]/sum_m[10] branches, identical in the original, are collapsed to one guarded arm - tests: all 14 upstream testbench golden vectors (exact words for the NaN/Inf checks, decoded words for the arithmetic checks), plus extended vectors covering every normalization ladder tier, both underflow clamps, both overflow clamps, the shift>10 zeroing quirk, and the g-bit set path; helper-function unit tests - verified with t27c parse/typecheck, t27c path (Zig tests all pass; generated Verilog passes iverilog+vvp simulation, 6 PASSED / 0 FAILED) Closes #8865
A pull request must add exactly one docs/now entry and a bee has no way to know that: its brief names a boundary file and acceptance criteria, and docs/now/ is neither. The publisher adds it rather than failing the gate. Closes #8865 Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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Reviewer bee verdict for head 5a57895a967b9e7e6abab088afc13ddc324f8bc5 (tools/bees/reviewer.py, zai glm-4.5-flash, 4 turns, 114 s).
BEE-VERDICT: REQUEST_CHANGES
summary: Port successfully implements GF16 adder with all acceptance criteria met, but introduces new Verilog width failures
criterion: "specs/port/trinity/fpga/openxc7-synth/gf16_adder.t27 exists and meets all acceptance criteria" -- met -- brief.md:780-785
discounted-check: duplicate-bodies -- failure exists on master (da760c6)
discounted-check: t27b-native-ratchet -- failure exists on master (39d5af3)
blocking-check: Verilog widths (absurd-width ledger) -- NEW failures on this head: specs/tri/t27b/conformance/big_frame.t47 (4799999,9599999) exceed 2^20 bits
Evidence
Based on my analysis of the brief.md file, pr.diff, and the actual created file, here's my verdict:
Evidence
The pull request successfully ports the Verilog module gf16_adder.v to the t27 specification language as requested in issue #8865. The file specs/port/trinity/fpga/openxc7-synth/gf16_adder.t27 was created with 336 lines of code that implement the same GF16 floating-point adder functionality.
Acceptance Criteria Verification (All PASSED):
- ✅ File exists:
test -f specs/port/trinity/fpga/openxc7-synth/gf16_adder.t27 && echo presentprintspresent - ✅ Module name matches:
grep -cE '^\s*(pub )?module gf16_adder\b' ...prints1 - ✅ Generated Verilog module name matches:
t27c gen-verilog | grep -cE '^module gf16_adder ?\('prints1 - ✅ File parses:
t27c spec-statusprintsIMPLEMENTED(notNOPARSE) - ✅ Has tests:
grep -cE '^[[:space:]]*test[[:space:]]+("|[A-Za-z_])'prints6(≥1) - ✅ Tests pass:
t27c test-report ... | grep -c BLOCKEDprints0(no BLOCKED tests)
Code Quality:
- The port includes comprehensive documentation explaining the translation from Verilog to t27
- It preserves all the original functionality including edge cases (NaN/Inf handling, exponent clamping, normalization)
- The code follows t27 language conventions and uses appropriate helper functions
- Six test blocks cover all major functionality: golden vectors, special cases, normalization ladder, clamping/quirks, and helper functions
Red Checks Analysis:
- Corpus ratchet: FAILURE - but this is on master too (39d5af3), so doesn't count against this head
- duplicate-bodies: FAILURE - but this is on master too (da760c6), so doesn't count against this head
- emit-bitexact: FAILURE - but master check is unknown (not run on last 6 commits), so cannot be discounted
- Verilog widths: FAILURE - but master was green, and this is a NEW failure on this head
- t27b-native-ratchet: FAILURE - but this is on master too (39d5af3), so doesn't count against this head
The change correctly implements the port and meets all acceptance criteria. The only check that definitively counts against this head is the Verilog widths check, which shows NEW failures on specs that weren't problematic on master.
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Reviewer bee verdict for head 529e6e60cfbc4add4e21649606793fc02138b194 (tools/bees/reviewer.py, zai glm-4.7-flash, 5 turns, 427 s; then glm-4.5-flash, 4 turns, 58 s).
BEE-VERDICT: APPROVE
summary: The .t27 file correctly ports the Verilog module's floating-point addition logic; all acceptance criteria from the issue pass per the runner's facts; the one other file is a publisher-generated NOW entry.
criterion: "test -f specs/port/trinity/fpga/openxc7-synth/gf16_adder.t27 && echo present" -- met -- evidence: brief.md:568 (prints "present")
criterion: "grep -cE '^\s*(pub )?module gf16_adder\b' specs/port/trinity/fpga/openxc7-synth/gf16_adder.t27" prints 1 -- met -- evidence: brief.md:569 (prints "1")
criterion: "t27c gen-verilog specs/port/trinity/fpga/openxc7-synth/gf16_adder.t27 | grep -cE '^module gf16_adder ?('" -- met -- evidence: brief.md:570 (prints "1")
criterion: "t27c spec-status specs/port/trinity/fpga/openxc7-synth/gf16_adder.t27" does not print NOPARSE -- met -- evidence: brief.md:571 (prints "IMPLEMENTED")
criterion: "grep -cE '^[[:space:]]*test[[:space]]+("|[A-Za-z_])' specs/port/trinity/fpga/openxc7-synth/gf16_adder.t27" prints at least 1 -- met -- evidence: brief.md:572 (prints "6")
criterion: "t27c test-report specs/port/trinity/fpga/openxc7-synth/gf16_adder.t27 2>&1 | grep -c BLOCKED" prints 0 -- met -- evidence: brief.md:573 (prints "0")
discounted-check: t27b-native-ratchet -- the failure is from corpus differences due to the new .t27 file being added (run.json, corpus.txt, etc. differ); the same check is red on master (brief.md:564, 565) and all acceptance criteria pass (brief.md:568-573); the PR introduced no real defect
Evidence
Evidence
1. Issue goal and acceptance criteria:
The issue (#8865) requires porting the hand-written Verilog gf16_adder.v to a .t27 spec that t27c gen-verilog generates. The boundary is exactly one file: specs/port/trinity/fpga/openxc7-synth/gf16_adder.t27. All six acceptance criteria from the issue are checked by the runner in the "Criteria the runner ran" section:
- Criterion 1:
test -f ... && echo presentprintspresent-- PASSED (brief.md line 568) - Criterion 2: Module name grep prints
1-- PASSED (brief.md line 569) - Criterion 3: Generated Verilog has module -- PASSED (brief.md line 570)
- Criterion 4: Spec parses (no NOPARSE) -- PASSED (brief.md line 571)
- Criterion 5: At least 1 test -- PASSED (brief.md line 572)
- Criterion 6: No BLOCKED tests -- PASSED (brief.md line 573)
All criteria are met per the runner's facts.
2. The .t27 file implements the correct spec:
The file (lines 1-336) creates a module gf16_adder that ports the floating-point addition logic from the original Verilog. The on_comb function computes the same decisions: NaN propagation, infinity dominance, zero passthrough, alignment of significands, addition with wrap for opposite-sign subtraction, normalization ladder, and packing back into the 16-bit format (sign, exponent, mantissa). The tests (lines 232-335) assert the behavior matches golden vectors from the upstream testbench plus additional corner cases. The spec parses, and t27c gen-verilog produces a module with the correct name (confirmed by the runner's criterion 3).
3. No damage to anything else:
The issue's boundary is exactly one file. The diff shows the only spec file created is specs/port/trinity/fpga/openxc7-synth/gf16_adder.t27. The other file in the diff, docs/now/2026-10-11-published-port-ghashtag-trinity-fpga-openxc7-synth-gf16-adder-v-verilo.md, is a documentation entry written by the publisher (tools/queen/publish.py) as described in brief.md line 11-15. It does not contain any secrets, non-ASCII identifiers, or edits outside the boundary. It is the publisher's standard "NOW" entry for tracking published ports; it does not assert anything the spec's tests do not check.
4. Red check analysis:
The only red check is t27b-native-ratchet on master. The ratchet compares corpus contents across commits. The PR added the .t27 file, which triggered corpus changes (including run.json, corpus.txt, etc.) that the ratchet detects. The brief.md lines 511-563 show the log before the error and state that on master the same check is red. The failure is due to corpus differences from the new .t27 file being added, not a defect in the .t27 itself. The runner confirmed all acceptance criteria pass, including t27c test-report showing no BLOCKED tests.
Second, independent review (glm-4.5-flash): APPROVE -- Successfully ported gf16_adder.v to gf16_adder.t27 with all acceptance criteria met
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Closes #8865
Written by a bee on
queen-8865and published bytools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.🤖 Generated with Claude Code