Port gHashTag/trinity:fpga/openxc7-synth/DSP48E1_mock.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/DSP by gHashTag · Pull Request #7970 · gHashTag/t27

gHashTag · 2026-10-08T23:52:37Z

Written by a bee on queen-7942 and published by tools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.

1 file changed, 172 insertions(+)

🤖 Generated with Claude Code

Re-authors the hand-written Verilog DSP48E1 mock (a0d149e71560) as a .t27 spec: the full DSP48E1 parameter set as module consts, the behavioural model as pure functions (18x18 multiply with the original's A[17:0]/B[17:0] slicing, m_reg/p_reg update semantics with the mock's !RSTP/!RSTM reset-wins-over-enable polarity, P selected by PREG, unused outputs hardwired low), an on_comb data boundary, and six test blocks asserting the values the original produces. t27c parse/typecheck: 0 errors, 0 warnings; test-report: 6 pass, 0 vacuous; coverage 10/10; parse-complete: no truncation; gen-verilog emits module DSP48E1, icarus-lowerable. Closes #7942

A pull request must add exactly one docs/now entry and a bee has no way to know that: its brief names a boundary file and acceptance criteria, and docs/now/ is neither. The publisher adds it rather than failing the gate. Closes #7942 Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>

github-actions · 2026-10-08T23:53:51Z

PR Dashboard

Generated at: 2026-10-08 23:53:43 UTC

Port gHashTag/trinity:fpga/openxc7-synth/DSP48E1_mock.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/DSP #7970 Port gHashTag/trinity:fpga/openxc7-synth/DSP48E1_mock.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/DSP | Created: 2026-10-08 | Updated: 2026-10-08 | 23 failing / 28 total
Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-07/src/cover_decoy_ratio_governor.rs (Rust, 1 function) to specs/por #7969 Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-07/src/cover_decoy_ratio_governor.rs (Rust, 1 function) to specs/por | Created: 2026-10-08 | Updated: 2026-10-08 | 21 failing / 29 total
Port gHashTag/trinity:fpga/openxc7-synth/dsp_mul.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/dsp_mul. #7968 Port gHashTag/trinity:fpga/openxc7-synth/dsp_mul.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/dsp_mul. | Created: 2026-10-08 | Updated: 2026-10-08 | 13 failing / 29 total
specs(tools/tri): real tests for 10 tool cards, misread to red (Closes #7951) #7958 specs(tools/tri): real tests for 10 tool cards, misread to red (Closes #7951) | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 31 total
policy: exception for tools/jtag/mpsse_jtag.py so B2 reads libftdi on Linux (Refs #7927) #7928 policy: exception for tools/jtag/mpsse_jtag.py so B2 reads libftdi on Linux (Refs #7927) | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 24 total
Port gHashTag/trinity:fpga/rtl/fpga_test_reporter.v (Verilog, 1 module) to specs/port/trinity/fpga/rtl/fpga_test_reporte #7926 Port gHashTag/trinity:fpga/rtl/fpga_test_reporter.v (Verilog, 1 module) to specs/port/trinity/fpga/rtl/fpga_test_reporte | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 29 total
t27b: std.math.inf, std.math.log with base e, std.math.log1p and an f64 @round, from libm_plan.t27 (Closes #7923) #7925 t27b: std.math.inf, std.math.log with base e, std.math.log1p and an f64 @round, from libm_plan.t27 (Closes #7923) | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 40 total
t27b: a call of a fn returning a float is spelled a float in x as T, from float_as_plan.t27 (Closes #7805) #7924 t27b: a call of a fn returning a float is spelled a float in x as T, from float_as_plan.t27 (Closes #7805) | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 42 total
Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-05/src/store_compaction_integrity_guard.rs (Rust, 1 function) to spe #7920 Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-05/src/store_compaction_integrity_guard.rs (Rust, 1 function) to spe | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 29 total
t27b: @log, @log2 and @log10 of an f32 call t27 ports of compiler_rt (Closes #7822) #7918 t27b: @log, @log2 and @log10 of an f32 call t27 ports of compiler_rt (Closes #7822) | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 42 total
t27b: a module var of an optional type that starts as null (Closes #7910) #7913 t27b: a module var of an optional type that starts as null (Closes #7910) | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 40 total
t27b: a local bound to an array repeat [v; n] and passed as [N]T is that array, as gen-zig prints .{ v } ** n (Closes #7909) #7912 t27b: a local bound to an array repeat [v; n] and passed as [N]T is that array, as gen-zig prints .{ v } ** n (Closes #7909) | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 41 total
t27b: @intCast as an array index or a slice bound takes Zig's usize, from int_cast_plan.t27 (Closes #7902) #7905 t27b: @intCast as an array index or a slice bound takes Zig's usize, from int_cast_plan.t27 (Closes #7902) | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 42 total
gen-ts: lower the bodies of pure functions #7872 gen-ts: lower the bodies of pure functions | Created: 2026-10-08 | Updated: 2026-10-08 | 4 failing / 42 total
t27b: == and != between pointers and optional pointers compare addresses, from a t27 plan (Closes #7742) #7831 t27b: == and != between pointers and optional pointers compare addresses, from a t27 plan (Closes #7742) | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 40 total
Port bootstrap/src/compiler.rs lines 23970-24090 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/return_unsized #7797 Port bootstrap/src/compiler.rs lines 23970-24090 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/return_unsized | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 29 total
Port gHashTag/trios:crates/trios-cli/src/cmd/issue.rs (Rust, 2 functions) to specs/port/trios/crates/trios-cli/src/cmd/i #7795 Port gHashTag/trios:crates/trios-cli/src/cmd/issue.rs (Rust, 2 functions) to specs/port/trios/crates/trios-cli/src/cmd/i | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 29 total
Port gHashTag/trinity:fpga/gf16-pipelined/gf16_dot4_p.v (Verilog, 1 module) to specs/port/trinity/fpga/gf16-pipelined/gf #7734 Port gHashTag/trinity:fpga/gf16-pipelined/gf16_dot4_p.v (Verilog, 1 module) to specs/port/trinity/fpga/gf16-pipelined/gf | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 29 total
fpga: systolic wavefront array spec -- matrix multiply as a schedule (for the ai-accelerator course) #7719 fpga: systolic wavefront array spec -- matrix multiply as a schedule (for the ai-accelerator course) | Created: 2026-10-08 | Updated: 2026-10-08 | 5 failing / 37 total
Port scripts/gen_w328.py (Python, 1 function) to specs/port/scripts/gen_w328.t27 #7709 Port scripts/gen_w328.py (Python, 1 function) to specs/port/scripts/gen_w328.t27 | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
Port fpga/verilog/gft_sadd_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_sadd_jtag.t27 #7708 Port fpga/verilog/gft_sadd_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_sadd_jtag.t27 | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 29 total
Port gHashTag/trinity:fpga/openxc7-synth/quantum_bridge_zero.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-sy #7707 Port gHashTag/trinity:fpga/openxc7-synth/quantum_bridge_zero.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-sy | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
Port gHashTag/trinity:src/tri/author_attribution_guard.zig (Zig, 2 functions) to specs/port/trinity/src/tri/author_attri #7689 Port gHashTag/trinity:src/tri/author_attribution_guard.zig (Zig, 2 functions) to specs/port/trinity/src/tri/author_attri | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 29 total
Port gHashTag/trinity:src/vibeec/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity/src/vibeec/bogatyrs #7644 Port gHashTag/trinity:src/vibeec/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity/src/vibeec/bogatyrs | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
Port gHashTag/trios:crates/trios-mcp/rings/SR-01/src/audits_new.rs (Rust, 4 functions) to specs/port/trios/crates/trios- #7643 Port gHashTag/trios:crates/trios-mcp/rings/SR-01/src/audits_new.rs (Rust, 4 functions) to specs/port/trios/crates/trios- | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
Port gHashTag/trinity:src/phi-engine/vibeec_original/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity #7624 Port gHashTag/trinity:src/phi-engine/vibeec_original/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity | Created: 2026-10-07 | Updated: 2026-10-07 | 2 failing / 31 total
Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-05/src/envelope_size_distribution_uniformity.rs (Rust, 1 function) t #7623 Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-05/src/envelope_size_distribution_uniformity.rs (Rust, 1 function) t | Created: 2026-10-07 | Updated: 2026-10-07 | 2 failing / 31 total
Implement the 1 empty function body in specs/test_framework/graph_drift_detection.t27 #7613 Implement the 1 empty function body in specs/test_framework/graph_drift_detection.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 4 failing / 29 total
Port fpga/verilog/gft_dup_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_dup_jtag.t27 #7612 Port fpga/verilog/gft_dup_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_dup_jtag.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 29 total
Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-04/src/padding_metadata_leak_guard.rs (Rust, 1 function) to specs/po #7582 Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-04/src/padding_metadata_leak_guard.rs (Rust, 1 function) to specs/po | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 29 total
Port scripts/gen_w376.py (Python, 1 function) to specs/port/scripts/gen_w376.t27 #7568 Port scripts/gen_w376.py (Python, 1 function) to specs/port/scripts/gen_w376.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 29 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/db/queen-pool.ts (TypeScript, 3 functions) to specs/port/ #7567 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/db/queen-pool.ts (TypeScript, 3 functions) to specs/port/ | Created: 2026-10-07 | Updated: 2026-10-07 | 4 failing / 29 total
Port scripts/gen_w369.py (Python, 1 function) to specs/port/scripts/gen_w369.t27 #7555 Port scripts/gen_w369.py (Python, 1 function) to specs/port/scripts/gen_w369.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 29 total
Port scripts/gen_w372.py (Python, 1 function) to specs/port/scripts/gen_w372.t27 #7554 Port scripts/gen_w372.py (Python, 1 function) to specs/port/scripts/gen_w372.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 4 failing / 29 total
Port gHashTag/trinity:src/depin/swarm_watch.zig (Zig, 2 functions) to specs/port/trinity/src/depin/swarm_watch.t27 #7553 Port gHashTag/trinity:src/depin/swarm_watch.zig (Zig, 2 functions) to specs/port/trinity/src/depin/swarm_watch.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 29 total
Port gHashTag/trios:tools/acm_ae_check/src/main.rs (Rust, 1 function) to specs/port/trios/tools/acm_ae_check/src/main.t2 #7552 Port gHashTag/trios:tools/acm_ae_check/src/main.rs (Rust, 1 function) to specs/port/trios/tools/acm_ae_check/src/main.t2 | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 29 total
Port fpga/verilog/gft_kat_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_kat_jtag.t27 #7540 Port fpga/verilog/gft_kat_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_kat_jtag.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 29 total
Port gHashTag/trios:crates/trios-trainer/src/data.rs (Rust, 7 functions) to specs/port/trios/crates/trios-trainer/src/da #7539 Port gHashTag/trios:crates/trios-trainer/src/data.rs (Rust, 7 functions) to specs/port/trios/crates/trios-trainer/src/da | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 29 total
t27c: refuse a malformed number literal by name, read 0o as octal (Closes #7319, Closes #2645) #7421 t27c: refuse a malformed number literal by name, read 0o as octal (Closes #7319, Closes #2645) | Created: 2026-10-07 | Updated: 2026-10-07 | 14 failing / 43 total
gen-c: run defer at every exit of its block (Closes #7352) #7406 gen-c: run defer at every exit of its block (Closes #7352) | Created: 2026-10-07 | Updated: 2026-10-07 | 36 failing / 42 total
tri: test runs the tests; mutate plant names what a one-line mutant turns red #7400 tri: test runs the tests; mutate plant names what a one-line mutant turns red | Created: 2026-10-07 | Updated: 2026-10-08 | 2 failing / 37 total
t27b: an array length written as a constant expression (Closes #7347) #7382 t27b: an array length written as a constant expression (Closes #7347) | Created: 2026-10-07 | Updated: 2026-10-07 | 12 failing / 42 total
Port scripts/gen_w370.py (Python, 1 function) to specs/port/scripts/gen_w370.t27 #7335 Port scripts/gen_w370.py (Python, 1 function) to specs/port/scripts/gen_w370.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 7 failing / 29 total
Port fpga/verilog/gft_signed_mac_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_signed_mac_jtag.t27 #7333 Port fpga/verilog/gft_signed_mac_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_signed_mac_jtag.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 0 failing / 1 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/tools/acl/acl-edit-distance.ts (TypeScript, 1 function) to sp #7286 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/tools/acl/acl-edit-distance.ts (TypeScript, 1 function) to sp | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 30 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/browser/dom.ts (TypeScript, 3 functions) to specs/port/browse #7285 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/browser/dom.ts (TypeScript, 3 functions) to specs/port/browse | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 30 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/db/index.ts (TypeScript, 4 functions) to specs/port/brows #7284 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/db/index.ts (TypeScript, 4 functions) to specs/port/brows | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 30 total
Port scripts/gen_w375.py (Python, 1 function) to specs/port/scripts/gen_w375.t27 #7280 Port scripts/gen_w375.py (Python, 1 function) to specs/port/scripts/gen_w375.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 29 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/routes/credits.ts (TypeScript, 1 function) to specs/port/ #7279 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/routes/credits.ts (TypeScript, 1 function) to specs/port/ | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 30 total
Port gHashTag/trinity:src/tri/gen_benchmark.zig (Zig, 2 functions) to specs/port/trinity/src/tri/gen_benchmark.t27 #7278 Port gHashTag/trinity:src/tri/gen_benchmark.zig (Zig, 2 functions) to specs/port/trinity/src/tri/gen_benchmark.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 2 failing / 29 total

Summary

Status	Count
Total Open PRs	50
PRs with Failing Checks	46
PRs with All Checks Green	4
READY	1
FAILING	46
PENDING	0
NO CHECKS YET	0

These columns do not partition: 1 + 46 + 0 + 0 = 47, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

⚠️ STALE -- sha256(compiler.rs)=3c0ade9e73e4 != manifest seal=87e5cbd3ad94.
The committed NMSE numbers were certified against an older compiler.rs.
Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

Trinity Bee and others added 2 commits October 8, 2026 22:07

github-actions Bot mentioned this pull request Oct 8, 2026

Port gHashTag/trinity:fpga/openxc7-synth/dsp_mul.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/dsp_mul. #7968

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Port gHashTag/trinity:fpga/openxc7-synth/DSP48E1_mock.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/DSP - #7970

Port gHashTag/trinity:fpga/openxc7-synth/DSP48E1_mock.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/DSP#7970
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