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specs/port/fpga: ported FPGA tests are read again (#5728) - #5729

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specfix/port-fpga-tests-5728
Oct 3, 2026
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dmitrii-f-t27 merged 3 commits into
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specfix/port-fpga-tests-5728

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@dmitrii-f-t27 dmitrii-f-t27 commented Oct 3, 2026 •

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Closes #5728

  • t27c parse-complete --show now prints nothing discarded for e8m0_jtag (was 312 tokens), link_node (219), ternary_mac_demo_top (435) and uart_echo_top (422).
  • Tests in the generated Zig: 3→18, 16→16 (8 had empty bodies; now 8 call link_node_process), 3→9 and 3→15. t27c test-report gives 18/18, 16/16, 9/9 and 15/15 (master: 2/3, 16/16, 2/3, 2/3).
  • Port bugs the recovered tests exposed are fixed against the original Verilog in history. In e8m0_jtag, the capture word now places the flag bits correctly and the shift register shifts right (sr <= {tdi, sr[31:1]}). In ternary_mac_demo_top, w_code for 2'b01 is [1, 0]. Three wrong expectations are corrected, each with a comment: the TDO bit of 0xA5A531BC, and the one-step counter ticks in ternary_mac_demo_top and uart_echo_top. No check was deleted.
  • Typecheck is OK with 0 warnings and zig ast-check is clean, on master and here. None of these specs has a seal.
  • Ledger: the four parse-no-discard entries are removed and max_entries drops by four, to 126 on top of specs/numeric: GF8/20/24/32 invariants check concrete points instead of prose the parser drops #5702 (which had already lowered it to 130; master is merged in). A local t27c suite --ratchet --corpus-only reports RATCHET: CLEAN. check_assertionless_spec_tests.py is OK.
  • Left out: gft_dup2_jtag.t27 from the same batch. Its tests loop 2^24 steps and assume the beat counts raw steps rather than slow-clock ticks, so it needs a test redesign, not a syntax repair.

🤖 Generated with Claude Code

Four ported FPGA specs wrote their BDD tests in Zig syntax (glued
`test_name`, `T{ .f = v }`, `[0] ** N`, tuple destructuring, bare enum
literals). The parser discarded 312 + 219 + 435 + 422 tokens, so the
generated Zig kept only the first few tests. The tests are now t27.
The port bugs they expose are fixed against the original Verilog: the
e8m0 capture bit packing and the shift direction, and the w_code bit order
in ternary_mac_demo_top. Three wrong expectations are corrected, each
with a comment. The four parse-no-discard ledger entries are removed and
max_entries goes from 134 to 130.

Closes #5728

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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PR Dashboard

Generated at: 2026-10-03 10:12:02 UTC

Summary

Status Count
Total Open PRs 39
PRs with Failing Checks 36
PRs with All Checks Green 3
READY 1
FAILING 36
PENDING 0
NO CHECKS YET 0

These columns do not partition: 1 + 36 + 0 + 0 = 37, and there are 39 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=b45a356c2eb6 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

…0 -> 126

#5702 also lowered the cap from 134 to 130, so the two edits merged
silently to 130. This branch removes four more entries, so the cap is 126.

Closes #5728

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Closes #5728

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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This notebook contains session context, decisions, and artifacts for this work.

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PR Dashboard

Generated at: 2026-10-03 10:28:27 UTC

Summary

Status Count
Total Open PRs 45
PRs with Failing Checks 41
PRs with All Checks Green 4
READY 1
FAILING 41
PENDING 0
NO CHECKS YET 0

These columns do not partition: 1 + 41 + 0 + 0 = 42, and there are 45 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=b45a356c2eb6 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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Four ported FPGA specs drop most of their tests: Zig test syntax the parser cannot read

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