Port scripts/lee_monte_carlo_baseline.py (Python, 2 functions) to specs/port/scripts/lee_monte_carlo_baseline.t27 by gHashTag · Pull Request #7020 · gHashTag/t27

gHashTag · 2026-10-06T17:59:44Z

Written by a bee on queen-5995 and published by tools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.

1 file changed, 135 insertions(+)

🤖 Generated with Claude Code

The port keeps the two functions of the original with their names and decisions: evaluate_expression (line 29: relative error abs(y - value) / value against the 0.001 threshold, 1 on a hit, 0 otherwise) and search_trinity_basis (line 37: the ten candidate lambdas of the original list enumerated inline in the original order, hits summed). The script's plumbing - loading research/lee-analysis/search_space_count.json, generating the random targets with numpy, printing, and writing monte_carlo_results.json - stays in Python and is not ported. np.sin and np.cos have no .t27 builtins, so the two trig candidates are carried as Taylor series with range reduction into [-PI, PI]. Four test blocks assert on the threshold decision (including the strict 0.001 boundary), the hit counting over the ten candidates, abs(), and the trig series. The generated Zig has no undefined and no not-yet-implemented markers, so it compiles clean under zig 0.16. Closes #5995

A pull request must add exactly one docs/now entry and a bee has no way to know that: its brief names a boundary file and acceptance criteria, and docs/now/ is neither. The publisher adds it rather than failing the gate. Closes #5995 Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>

github-actions · 2026-10-06T18:39:22Z

PR Dashboard

Generated at: 2026-10-06 18:39:15 UTC

Port gHashTag/trinity:fpga/openxc7-synth/blink_test_top.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/b #7040 Port gHashTag/trinity:fpga/openxc7-synth/blink_test_top.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/b | Created: 2026-10-06 | Updated: 2026-10-06 | 27 failing / 28 total
Port tools/backend_parity_table.py (Python, 4 functions) to specs/port/tools/backend_parity_table.t27 #7039 Port tools/backend_parity_table.py (Python, 4 functions) to specs/port/tools/backend_parity_table.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 27 failing / 28 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/terminal/terminal-session.ts (TypeScript, 3 func #7038 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/terminal/terminal-session.ts (TypeScript, 3 func | Created: 2026-10-06 | Updated: 2026-10-06 | 27 failing / 28 total
Port fpga/vivado/blinky.v (Verilog, 1 module) to specs/port/fpga/vivado/blinky.t27 #7037 Port fpga/vivado/blinky.v (Verilog, 1 module) to specs/port/fpga/vivado/blinky.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 27 failing / 28 total
Port gHashTag/trios:crates/trios-trainer/src/validation.rs (Rust, 2 functions) to specs/port/trios/crates/trios-trainer/ #7036 Port gHashTag/trios:crates/trios-trainer/src/validation.rs (Rust, 2 functions) to specs/port/trios/crates/trios-trainer/ | Created: 2026-10-06 | Updated: 2026-10-06 | 27 failing / 28 total
Port gHashTag/trios:crates/trios-cli/src/cmd/run.rs (Rust, 5 functions) to specs/port/trios/crates/trios-cli/src/cmd/run #7035 Port gHashTag/trios:crates/trios-cli/src/cmd/run.rs (Rust, 5 functions) to specs/port/trios/crates/trios-cli/src/cmd/run | Created: 2026-10-06 | Updated: 2026-10-06 | 27 failing / 28 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/clients/llm/refine-prompt.ts (TypeScript, 2 functions) to #7034 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/clients/llm/refine-prompt.ts (TypeScript, 2 functions) to | Created: 2026-10-06 | Updated: 2026-10-06 | 26 failing / 28 total
Port tools/fuzz_trainer.py (Python, 4 functions) to specs/port/tools/fuzz_trainer.t27 #7033 Port tools/fuzz_trainer.py (Python, 4 functions) to specs/port/tools/fuzz_trainer.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 26 failing / 28 total
Port gHashTag/trinity:fpga/openxc7-synth/quantum_bridge_top.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-syn #7032 Port gHashTag/trinity:fpga/openxc7-synth/quantum_bridge_top.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-syn | Created: 2026-10-06 | Updated: 2026-10-06 | 25 failing / 28 total
Port gHashTag/trinity:src/tri/sacred_constants.zig (Zig, 1 function) to specs/port/trinity/src/tri/sacred_constants.t27 #7031 Port gHashTag/trinity:src/tri/sacred_constants.zig (Zig, 1 function) to specs/port/trinity/src/tri/sacred_constants.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 25 failing / 28 total
Port scripts/lee_monte_carlo_baseline.py (Python, 2 functions) to specs/port/scripts/lee_monte_carlo_baseline.t27 #7020 Port scripts/lee_monte_carlo_baseline.py (Python, 2 functions) to specs/port/scripts/lee_monte_carlo_baseline.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 15 failing / 29 total
Port gHashTag/trinity:src/tri/gen_sigmoid.zig (Zig, 2 functions) to specs/port/trinity/src/tri/gen_sigmoid.t27 #7019 Port gHashTag/trinity:src/tri/gen_sigmoid.zig (Zig, 2 functions) to specs/port/trinity/src/tri/gen_sigmoid.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 8 failing / 29 total
Port gHashTag/trios:crates/trios-ternary/rings/TR-01/src/lib.rs (Rust, 2 functions) to specs/port/trios/crates/trios-ter #7018 Port gHashTag/trios:crates/trios-ternary/rings/TR-01/src/lib.rs (Rust, 2 functions) to specs/port/trios/crates/trios-ter | Created: 2026-10-06 | Updated: 2026-10-06 | 7 failing / 29 total
Port bootstrap/src/compiler.rs lines 1-264 (Rust, 3 functions) to specs/port/bootstrap/src/compiler/Node_default.t27 #7017 Port bootstrap/src/compiler.rs lines 1-264 (Rust, 3 functions) to specs/port/bootstrap/src/compiler/Node_default.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 6 failing / 29 total
Port bootstrap/src/check_calls.rs (Rust, 7 functions) to specs/port/bootstrap/src/check_calls.t27 #7016 Port bootstrap/src/check_calls.rs (Rust, 7 functions) to specs/port/bootstrap/src/check_calls.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 5 failing / 29 total
Port bootstrap/src/compiler.rs lines 28398-28603 (Rust, 5 functions) to specs/port/bootstrap/src/compiler/HwType_hw_widt #7015 Port bootstrap/src/compiler.rs lines 28398-28603 (Rust, 5 functions) to specs/port/bootstrap/src/compiler/HwType_hw_widt | Created: 2026-10-06 | Updated: 2026-10-06 | 6 failing / 29 total
Port gHashTag/trinity:src/api/depin_rest.zig (Zig, 2 functions) to specs/port/trinity/src/api/depin_rest.t27 #7014 Port gHashTag/trinity:src/api/depin_rest.zig (Zig, 2 functions) to specs/port/trinity/src/api/depin_rest.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 4 failing / 29 total
Port bootstrap/src/compiler.rs lines 30884-30976 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/LinkSection_te #7013 Port bootstrap/src/compiler.rs lines 30884-30976 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/LinkSection_te | Created: 2026-10-06 | Updated: 2026-10-06 | 4 failing / 29 total
Port fpga/vivado/gf16_top.v (Verilog, 1 module) to specs/port/fpga/vivado/gf16_top.t27 #7012 Port fpga/vivado/gf16_top.v (Verilog, 1 module) to specs/port/fpga/vivado/gf16_top.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 4 failing / 29 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/queen-lease.ts (TypeScript, 6 functions) to spec #7011 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/queen-lease.ts (TypeScript, 6 functions) to spec | Created: 2026-10-06 | Updated: 2026-10-06 | 4 failing / 29 total
t27b: untyped var from an integer literal, unread undefined const (StmtLocal) (Closes #6995) #7010 t27b: untyped var from an integer literal, unread undefined const (StmtLocal) (Closes #6995) | Created: 2026-10-06 | Updated: 2026-10-06 | 11 failing / 39 total
crm-story-reel v29: brand kit on every preview and the rendered end card #7009 crm-story-reel v29: brand kit on every preview and the rendered end card | Created: 2026-10-06 | Updated: 2026-10-06 | 3 failing / 25 total
spec(queen): actors control lane, call, backoff, hung turn, dead letters (Closes #6972 #6974 #6975 #6976 #6990 #6991 #6992) #7001 spec(queen): actors control lane, call, backoff, hung turn, dead letters (Closes #6972 #6974 #6975 #6976 #6990 #6991 #6992) | Created: 2026-10-06 | Updated: 2026-10-06 | 4 failing / 29 total
crm-story-reel v28: a retry renders only the empty clip slots #7000 crm-story-reel v28: a retry renders only the empty clip slots | Created: 2026-10-06 | Updated: 2026-10-06 | 2 failing / 25 total
t27b: an untyped var takes the reference's u32/u64 width; an untyped undefined const is accepted (Closes #6967) #6998 t27b: an untyped var takes the reference's u32/u64 width; an untyped undefined const is accepted (Closes #6967) | Created: 2026-10-06 | Updated: 2026-10-06 | 20 failing / 31 total
Port scripts/gen_w633.py (Python, 3 functions) to specs/port/scripts/gen_w633.t27 (Closes #6711) #6997 Port scripts/gen_w633.py (Python, 3 functions) to specs/port/scripts/gen_w633.t27 (Closes #6711) | Created: 2026-10-06 | Updated: 2026-10-06 | 27 failing / 30 total
fix(codegen): gen-rust enum order and gen-zig float-call cast (#6941) #6994 fix(codegen): gen-rust enum order and gen-zig float-call cast (#6941) | Created: 2026-10-06 | Updated: 2026-10-06 | 7 failing / 40 total
gen-verilog and gen-verilog-hir: hello_world.t27 output is refused by iverilog, verilator and yosys #6987 gen-verilog and gen-verilog-hir: hello_world.t27 output is refused by iverilog, verilator and yosys | Created: 2026-10-06 | Updated: 2026-10-06 | 3 failing / 29 total
Port bootstrap/src/compiler.rs lines 29796-29869 (Rust, 10 functions) to specs/port/bootstrap/src/compiler/HirIpCatalog_ #6986 Port bootstrap/src/compiler.rs lines 29796-29869 (Rust, 10 functions) to specs/port/bootstrap/src/compiler/HirIpCatalog_ | Created: 2026-10-06 | Updated: 2026-10-06 | 4 failing / 29 total
Port gHashTag/trinity:fpga/openxc7-synth/blink_fixed.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/blin #6985 Port gHashTag/trinity:fpga/openxc7-synth/blink_fixed.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/blin | Created: 2026-10-06 | Updated: 2026-10-06 | 2 failing / 29 total
Port bootstrap/src/compiler.rs lines 28704-28852 (Rust, 7 functions) to specs/port/bootstrap/src/compiler/HirClockDomain #6984 Port bootstrap/src/compiler.rs lines 28704-28852 (Rust, 7 functions) to specs/port/bootstrap/src/compiler/HirClockDomain | Created: 2026-10-06 | Updated: 2026-10-06 | 3 failing / 29 total
Port bootstrap/src/enrichment/mod.rs (Rust, 2 functions) to specs/port/bootstrap/src/enrichment/mod.t27 #6983 Port bootstrap/src/enrichment/mod.rs (Rust, 2 functions) to specs/port/bootstrap/src/enrichment/mod.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 3 failing / 29 total
Port bootstrap/src/compiler.rs lines 30624-30746 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/VcdVarKind_vcd #6982 Port bootstrap/src/compiler.rs lines 30624-30746 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/VcdVarKind_vcd | Created: 2026-10-06 | Updated: 2026-10-06 | 4 failing / 29 total
Port bootstrap/src/compiler.rs lines 29059-29184 (Rust, 7 functions) to specs/port/bootstrap/src/compiler/HirApbBridge_n #6981 Port bootstrap/src/compiler.rs lines 29059-29184 (Rust, 7 functions) to specs/port/bootstrap/src/compiler/HirApbBridge_n | Created: 2026-10-06 | Updated: 2026-10-06 | 3 failing / 29 total
spec(crm-story-reel): v27 gallery preview draws the render's end-card defaults (Refs #6973) #6980 spec(crm-story-reel): v27 gallery preview draws the render's end-card defaults (Refs #6973) | Created: 2026-10-06 | Updated: 2026-10-06 | 2 failing / 29 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/openclaw/claw-session.ts (TypeScript, 3 function #6979 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/openclaw/claw-session.ts (TypeScript, 3 function | Created: 2026-10-06 | Updated: 2026-10-06 | 2 failing / 29 total
Port gHashTag/trinity:src/server_main.zig (Zig, 1 function) to specs/port/trinity/src/server_main.t27 #6978 Port gHashTag/trinity:src/server_main.zig (Zig, 1 function) to specs/port/trinity/src/server_main.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 3 failing / 29 total
"Power analysis regression" is nine echo lines and never opens the file it names #6977 "Power analysis regression" is nine echo lines and never opens the file it names | Created: 2026-10-06 | Updated: 2026-10-06 | 4 failing / 36 total
feat(t27b): std.mem.eql/indexOf on byte slices and byte-array pointers (Closes #6961) #6970 feat(t27b): std.mem.eql/indexOf on byte slices and byte-array pointers (Closes #6961) | Created: 2026-10-06 | Updated: 2026-10-06 | 4 failing / 37 total
fix(numeric): settle gf16.t27 against FORMAT-SPEC-001 -- no subnormals, ties toward zero, NaN 0xFE01, exponent mask (#6940) #6969 fix(numeric): settle gf16.t27 against FORMAT-SPEC-001 -- no subnormals, ties toward zero, NaN 0xFE01, exponent mask (#6940) | Created: 2026-10-06 | Updated: 2026-10-06 | 27 failing / 30 total
Port bootstrap/src/cc_gate.rs (Rust, 4 functions) to specs/port/bootstrap/src/cc_gate.t27 #6960 Port bootstrap/src/cc_gate.rs (Rust, 4 functions) to specs/port/bootstrap/src/cc_gate.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 1 failing / 26 total
Port bootstrap/src/compiler.rs lines 30006-30113 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/AsmRelocEntry_ #6959 Port bootstrap/src/compiler.rs lines 30006-30113 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/AsmRelocEntry_ | Created: 2026-10-06 | Updated: 2026-10-06 | 3 failing / 26 total
gen-zig: a one-element array constant ([1]u32 = [48]) makes test-report BLOCK trinity specs/reproduce/contracts.t27 #6958 gen-zig: a one-element array constant ([1]u32 = [48]) makes test-report BLOCK trinity specs/reproduce/contracts.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 12 failing / 37 total
Port gHashTag/trinity:src/tri/gen_lockfree_stack.zig (Zig, 4 functions) to specs/port/trinity/src/tri/gen_lockfree_stack #6957 Port gHashTag/trinity:src/tri/gen_lockfree_stack.zig (Zig, 4 functions) to specs/port/trinity/src/tri/gen_lockfree_stack | Created: 2026-10-06 | Updated: 2026-10-06 | 2 failing / 26 total
Port gHashTag/trinity:src/cli/railway_deployment_create.zig (Zig, 1 function) to specs/port/trinity/src/cli/railway_depl #6956 Port gHashTag/trinity:src/cli/railway_deployment_create.zig (Zig, 1 function) to specs/port/trinity/src/cli/railway_depl | Created: 2026-10-06 | Updated: 2026-10-06 | 2 failing / 26 total
Port bootstrap/src/compiler.rs lines 29336-29485 (Rust, 7 functions) to specs/port/bootstrap/src/compiler/HirFormalConfi #6955 Port bootstrap/src/compiler.rs lines 29336-29485 (Rust, 7 functions) to specs/port/bootstrap/src/compiler/HirFormalConfi | Created: 2026-10-06 | Updated: 2026-10-06 | 2 failing / 26 total
Implement part 2 of 2 of the empty bodies in specs/depin/prove.t27 (3 functions) #6954 Implement part 2 of 2 of the empty bodies in specs/depin/prove.t27 (3 functions) | Created: 2026-10-06 | Updated: 2026-10-06 | 2 failing / 26 total
Four sources state the catalogue size and give four numbers: 109 is canonical, and nine repeated names are unexplained #6953 Four sources state the catalogue size and give four numbers: 109 is canonical, and nine repeated names are unexplained | Created: 2026-10-06 | Updated: 2026-10-06 | 4 failing / 28 total
Port fpga/verilog/gft_smul_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_smul_jtag.t27 #6952 Port fpga/verilog/gft_smul_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_smul_jtag.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 1 failing / 26 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/serialize-error.ts (TypeScript, 1 function) to specs/port #6951 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/serialize-error.ts (TypeScript, 1 function) to specs/port | Created: 2026-10-06 | Updated: 2026-10-06 | 1 failing / 26 total

Summary

Status	Count
Total Open PRs	50
PRs with Failing Checks	40
PRs with All Checks Green	10
READY	0
FAILING	40
PENDING	0
NO CHECKS YET	0

These columns do not partition: 0 + 40 + 0 + 0 = 40, and there are 50 open PRs. A PR is being counted twice or not at all.

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⚠️ STALE -- sha256(compiler.rs)=b23641f01baa != manifest seal=87e5cbd3ad94.
The committed NMSE numbers were certified against an older compiler.rs.
Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

Trinity Bee and others added 2 commits October 4, 2026 15:31

gHashTag enabled auto-merge (squash) October 7, 2026 07:24

gHashTag merged commit 129ee4c into master Oct 7, 2026
27 of 29 checks passed

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Port scripts/lee_monte_carlo_baseline.py (Python, 2 functions) to specs/port/scripts/lee_monte_carlo_baseline.t27 - #7020

Port scripts/lee_monte_carlo_baseline.py (Python, 2 functions) to specs/port/scripts/lee_monte_carlo_baseline.t27#7020
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