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Port fpga/verilog/gft_smul_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_smul_jtag.t27 - #6952
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…_jtag.t27 - Add module gft_smul_jtag with JTAG_CHAIN_N parameter - Define constants ONE=20480, TWO=20992, Z=0 for 16.16 floating-point format - Implement GFT multiplier simulation with proper test properties: - ZERO: smul(0, x) == 0 and smul(x, 0) == 0 - COMM: smul(live, TWO) == smul(TWO, live) - GOLD: smul(1.0, 1.0) == 1.0 (20480) - IND: smul(live, ONE) is non-zero and equals live - Add JTAG scan chain functionality with WORD v3 format - Include comprehensive tests for all properties and invariants - Generated Verilog matches original module name and interface Closes #5133
A pull request must add exactly one docs/now entry and a bee has no way to know that: its brief names a boundary file and acceptance criteria, and docs/now/ is neither. The publisher adds it rather than failing the gate. Closes #5133 Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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Reviewer bee verdict for head 31e04dfc0b90a448095f5bc5c517acfcb22668f3 (tools/bees/reviewer.py, zai glm-4.7-flash, 3 turns, 92 s; then glm-4.5-flash, 7 turns, 65 s).
BEE-VERDICT: APPROVE
summary: The PR ported the Verilog multiplier module to .t27 specification with 8 tests that validate the four key properties (ZERO, COMM, GOLD, IND). All 6 acceptance criteria pass and the change is confined to the single boundary file.
criterion: "test -f specs/port/fpga/verilog/gft_smul_jtag.t27 && echo present" -- met -- evidence: brief.md:526
criterion: "grep -cE '^\s*(pub )?module gft_smul_jtag\b' specs/port/fpga/verilog/gft_smul_jtag.t27" prints 1 -- met -- evidence: brief.md:527
criterion: "t27c gen-verilog ... | grep -cE '^module gft_smul_jtag ?('" prints 1 -- met -- evidence: brief.md:528
criterion: "t27c spec-status ... does not print NOPARSE" -- met -- evidence: brief.md:529
criterion: "grep -cE '^[[:space:]]*test[[:space:]]+("|[A-Za-z_])'" prints at least 1 -- met -- evidence: brief.md:530
criterion: "t27c test-report ... | grep -c BLOCKED" prints 0 -- met -- evidence: brief.md:531
discounted-check: spec-guards -- the check tests 9 unrelated spec-ring pairs across the entire codebase; the new gft_smul_jtag.t27 spec is not among them, and the differences shown (ring-092-rust, ring-096-rust, ring-097-rust) were already failing on master (evidence: brief.md:474, 493-511)
Evidence
Analysis
Acceptance Criteria Verification
1. File existence criterion
met -- test -f specs/port/fpga/verilog/gft_smul_jtag.t27 && echo present prints present
2. Module name criterion
met -- grep -cE '^\s*(pub )?module gft_smul_jtag\b' specs/port/fpga/verilog/gft_smul_jtag.t27 prints 1
3. Generated Verilog module name criterion
met -- t27c gen-verilog specs/port/fpga/verilog/gft_smul_jtag.t27 | grep -cE '^module gft_smul_jtag ?\(' prints 1
4. Parse criterion
met -- t27c spec-status specs/port/fpga/verilog/gft_smul_jtag.t27 prints IMPLEMENTED (not NOPARSE)
5. Tests present criterion
met -- grep -cE '^[[:space:]]*test[[:space:]]+("|[A-Za-z_])' specs/port/fpga/verilog/gft_smul_jtag.t27 prints 8
6. Test execution criterion
met -- t27c test-report specs/port/fpga/verilog/gft_smul_jtag.t27 2>&1 | grep -c BLOCKED prints 0
Do these meet the issue's stated goal?
Yes. The issue asks to port the hand-written Verilog module gft_smul_jtag.v to .t27 specification form. The PR creates specs/port/fpga/verilog/gft_smul_jtag.t27 containing:
- Constants matching the original (
JTAG_CHAIN_N = 3,ONE = 20480,TWO = 20992,Z = 0) - Test structure defining properties the original tests: ZERO, COMM, GOLD, IND
- Test functions that model multiplication behavior and assert expected properties
testblocks validating these properties
The t27c test-report output shows 0 BLOCKED, confirming the generated code compiles and all tests run.
Red checks analysis
There is 1 red check: spec-guards.
The log shows this check runs on the entire repository (9 spec-ring pairs). The PR only adds one new spec file. The check's output shows ring-092-rust, ring-096-rust, and ring-097-rust have differences, but these are pre-existing issues on master (as confirmed by "on master: master 96cf7c8: failure" in brief.md). The spec-guards check is checking 9 unrelated specs against 3 Rust rings, none of which is the new gft_smul_jtag.t27.
Second, independent review (glm-4.5-flash): APPROVE -- Successfully ported gft_smul_jtag.v to specs/port/fpga/verilog/gft_smul_jtag.t27 with all acceptance criteria met
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Closes #5133
Written by a bee on
queen-5133and published bytools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.🤖 Generated with Claude Code