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fix(t27c): gen refuses what typecheck refuses, 35 misread specs fixed (Closes #6446) - #6787
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A spec that `t27c typecheck` refuses now generates nothing on every gen path (gen, gen-c, gen-rust, gen-verilog, gen-verilog-hir, gen-verilog-for-simulation, gen-testbench, gen-js, gen-ts, gen-python, icarus-*, compile-all, compile-project, seal hashing and the HTTP server): stdout stays empty, the command exits non-zero and stderr carries the typecheck messages. There is no flag to skip it. Carries the gate from #6577 (rebased on master 5bad205) and adds the gen-testbench path it missed. The test moves into the existing harness bootstrap/tests/backend_behaviour.rs and reads two .t27 fixtures under bootstrap/tests/fixtures/gen_typecheck/ (a field with no type, and its well-formed twin as the negative control), so no new Rust file is added. `tri misread` ran its reproducer through gen-rust and gen-c and required it to generate; with the gate it must instead be refused, and the shape typecheck still accepts (`Vec<>`) is proven on a separate silent control. Owner approval: label owner-approved-foreign on #6446 (2026-10-06) for edits to existing Rust for this issue; the three paths are listed in tools/policy/foreign-exceptions.txt with that scope. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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October 6, 2026 12:09
This was referenced Oct 6, 2026
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Port scripts/tri_loop/claims.py (Python, 1 function) to specs/port/scripts/tri_loop/claims.t27
#6842
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Closes #6446
Refs #6488 #6092
Owner approval
On 2026-10-06 the owner put the label
owner-approved-foreignon issue #6446. That approves edits to existing Rust inbootstrap/(the t27c compiler) for this issue only. This PR carries the same label. It adds no new foreign-language source file: the only new files are two.t27fixtures.What changes
.t27, by fix(specs): the 28 specs typecheck refused while gen emitted them (Refs #6446) #6491 (28 specs) and fix(specs): the 8 specs the gen typecheck gate would refuse (Refs #6446) #6566 (8 specs). The labmisreadgate on master5bad20521reportspairs 0, refused 0, silent 0, so this PR has no spec left to fix.bootstrap/src/main.rs). A spec thattypecheckrefuses produces no output, a non-zero exit, and the messagetypecheck refused <path>: N error(s), so nothing is generated for it (#6446)followed by each error. There is no escape flag on the default path.gen,gen-c,gen-rust,gen-verilog,gen-verilog-hir,gen-verilog-for-simulation,gen-testbench,gen-js/gen-ts/gen-python,icarus-simulate,icarus-cocotb,compile-all,compile-project,seal, and the server's compile/gen/seal handlers.bench, the self-test andflatten, because they do not emit backend code.gen-testbench. This PR supersedes feat(t27c): every gen path runs typecheck first (Closes #6446) [needs owner label] #6577.bootstrap/tests/backend_behaviour.rs, the existing harness, with two.t27fixtures inbootstrap/tests/fixtures/gen_typecheck/):gen_rust_refuses_a_field_with_no_type: a spec withf : ,, which used to printpub f: ,and exit 0, now makesgen-rustfail with the typecheck message and empty stdout.every_gen_path_refuses_a_spec_typecheck_refuses: the same check across all nine gen commands.typecheck_and_gen_agree_on_the_gate_fixtures: the well-formed twin still passestypecheck,gen,gen-rustandgen-c, so the refusal comes from the gate and not from a broken binary.tri misreadcontrol (cli/tri/src/misread.rs, outsidebootstrap/, carried from feat(t27c): every gen path runs typecheck first (Closes #6446) [needs owner label] #6577). Its positive control fed a malformed spec throughgen-rust/gen-cand expected the misread. Under the gate that spec is now refused, so the control expects the refusal. A second control (Vec<>, which typecheck accepts) keeps proving the shape detector still fires. Without this edit,tri misreadwould report its own control as broken.tools/specs_generate_baseline.txt: the three fixtures that must never generate (damage_negative/neg_02,neg_05, and the new negative fixture) are listed with the gate's refusal.tools/policy/foreign-exceptions.txt:main.rs,backend_behaviour.rsandmisread.rsare listed for this issue only, with the approval cited. Remove those three lines after this merges.bootstrap/src/compiler.rsis unchanged, so the seal andFROZEN_HASHdo not move. The labfrozen-hashgate reports a match (3c78f3c7ffb7), so the CONTRIBUTING.md "Build speed" seal step was not needed.Measured (Railway t27c lab, debug t27c, every tracked
.t27)5bad205213e07a2890.t27filestypecheckgen-rustexit 0genexit 0gen-rustrefusals that name the gateOn master, these four specs were refused by typecheck yet generated anyway:
damage_negative/neg_02_match_armsdamage_negative/neg_05_raw_stringterminator/field_swallowterminator/unbalancedAll four are fixtures. No spec under
specs/changes behaviour: the corpus already typechecks after #6491/#6566.tri misreadis clean on both sides (0 silent, 0 refused), and with this branch its control is green.cargo test -p t27c --testswith the CI ratchet:zig_primitive_bindingsand oneicarus_lowerable).Lab gates for
3e07a2890: verdict greenfrozen-hash: okbuild: oksuite: RATCHET CLEANlean: okseal-currency: okseal-coverage: 1471 seals, 1329 hold, 142 known-brokenspecs-parse: okspecs-generate: 1386 specs, 1382 generate, 4 known-broken (listed in the baseline)misread: 0 silent, 0 refused🤖 Generated with Claude Code