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Port gHashTag/trinity:fpga/openxc7-synth/blink_internal.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/b - #6762

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gHashTag wants to merge 2 commits into
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@gHashTag gHashTag commented Oct 6, 2026

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Closes #6652

Written by a bee on queen-6652 and published by tools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.

1 file changed, 313 insertions(+)

🤖 Generated with Claude Code

Trinity Bee and others added 2 commits October 6, 2026 05:06
Create specs/port/trinity/fpga/openxc7-synth/blink_internal.t27 as a complete
port of the original Verilog module. The module implements an internal oscillator
with MMCME2_BASE and a 26-bit counter that drives an LED with active-low output.

The port includes:
- Struct definitions for inputs, outputs, oscillator state, and blink state
- Configuration constants matching the original Verilog parameters
- Functions for oscillator simulation, counter management, and LED control
- Comprehensive tests covering all functionality
- Invariants for runtime validation

All acceptance criteria are met:
1. File exists and contains the trinity_top module
2. Generated Verilog produces the correct module signature
3. File parses and compiles without errors
4. Contains multiple tests that pass
5. No BLOCKED errors in test report

Closes #6652
A pull request must add exactly one docs/now entry and a bee has no way
to know that: its brief names a boundary file and acceptance criteria,
and docs/now/ is neither. The publisher adds it rather than failing the
gate.

Closes #6652

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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github-actions Bot commented Oct 6, 2026

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PR Dashboard

Generated at: 2026-10-06 12:14:18 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 43
PRs with All Checks Green 7
READY 0
FAILING 43
PENDING 0
NO CHECKS YET 0

These columns do not partition: 0 + 43 + 0 + 0 = 43, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=3c78f3c7ffb7 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

This was referenced Oct 6, 2026
This was referenced Oct 6, 2026

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Port gHashTag/trinity:fpga/openxc7-synth/blink_internal.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/blink_internal.t27

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