Port fpga/verilog/ternary_mac_demo_top_v2.v (Verilog, 1 module) to specs/port/fpga/verilog/ternary_mac_demo_top_v2.t27 by gHashTag · Pull Request #6735 · gHashTag/t27

gHashTag · 2026-10-06T11:02:16Z

Written by a bee on queen-5024 and published by tools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.

1 file changed, 180 insertions(+)

🤖 Generated with Claude Code

…g/ternary_mac_demo_top_v2.t27 - Create ternary_mac_demo_top_v2.t27 module with same functionality as original Verilog - Define PRESCALE_BITS parameter and LED output ports - Implement STARTUPE2 primitive as undefined (hardware primitive) - Implement ternary_mac_demo_core function with expected LED behavior - Add comprehensive tests for all functions and invariants - Validate LED behavior: led_r23 blinks, led_t23 stays dark (theorem T3) - Include benchmarks for performance measurement Closes #5024

A pull request must add exactly one docs/now entry and a bee has no way to know that: its brief names a boundary file and acceptance criteria, and docs/now/ is neither. The publisher adds it rather than failing the gate. Closes #5024 Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>

github-actions · 2026-10-06T11:05:59Z

PR Dashboard

Generated at: 2026-10-06 11:05:53 UTC

Port bootstrap/src/compiler.rs lines 29935-30005 (Rust, 9 functions) to specs/port/bootstrap/src/compiler/AssembledInstr #6742 Port bootstrap/src/compiler.rs lines 29935-30005 (Rust, 9 functions) to specs/port/bootstrap/src/compiler/AssembledInstr | Created: 2026-10-06 | Updated: 2026-10-06 | 24 failing / 25 total
Port bootstrap/src/jwt.rs (Rust, 4 functions) to specs/port/bootstrap/src/jwt.t27 #6741 Port bootstrap/src/jwt.rs (Rust, 4 functions) to specs/port/bootstrap/src/jwt.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 24 failing / 25 total
Port bootstrap/src/phi_selfcheck.rs (Rust, 2 functions) to specs/port/bootstrap/src/phi_selfcheck.t27 #6740 Port bootstrap/src/phi_selfcheck.rs (Rust, 2 functions) to specs/port/bootstrap/src/phi_selfcheck.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 24 failing / 25 total
Port tools/verify_emit_bitexact.py (Python, 4 functions) to specs/port/tools/verify_emit_bitexact.t27 #6739 Port tools/verify_emit_bitexact.py (Python, 4 functions) to specs/port/tools/verify_emit_bitexact.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 24 failing / 25 total
Port scripts/pysr_trinity_blind_test_v2.py (Python, 1 function) to specs/port/scripts/pysr_trinity_blind_test_v2.t27 #6738 Port scripts/pysr_trinity_blind_test_v2.py (Python, 1 function) to specs/port/scripts/pysr_trinity_blind_test_v2.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 24 failing / 25 total
Port scripts/unified_search_all.py (Python, 2 functions) to specs/port/scripts/unified_search_all.t27 #6737 Port scripts/unified_search_all.py (Python, 2 functions) to specs/port/scripts/unified_search_all.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 24 failing / 25 total
Port fpga/vsa/temporal_heartbeat_top.v (Verilog, 1 module) to specs/port/fpga/vsa/temporal_heartbeat_top.t27 #6736 Port fpga/vsa/temporal_heartbeat_top.v (Verilog, 1 module) to specs/port/fpga/vsa/temporal_heartbeat_top.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 24 failing / 25 total
Port fpga/verilog/ternary_mac_demo_top_v2.v (Verilog, 1 module) to specs/port/fpga/verilog/ternary_mac_demo_top_v2.t27 #6735 Port fpga/verilog/ternary_mac_demo_top_v2.v (Verilog, 1 module) to specs/port/fpga/verilog/ternary_mac_demo_top_v2.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 23 failing / 25 total
Port fpga/vivado/matmul_serial_top.v (Verilog, 1 module) to specs/port/fpga/vivado/matmul_serial_top.t27 #6734 Port fpga/vivado/matmul_serial_top.v (Verilog, 1 module) to specs/port/fpga/vivado/matmul_serial_top.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 18 failing / 26 total
t27b checked: test blocks for 7 specs in specs/functions (1 of 5) #6733 t27b checked: test blocks for 7 specs in specs/functions (1 of 5) | Created: 2026-10-06 | Updated: 2026-10-06 | 19 failing / 26 total
feat(verified): run-level verdict rule (FR-004 of #6656, epic #6655) #6732 feat(verified): run-level verdict rule (FR-004 of #6656, epic #6655) | Created: 2026-10-06 | Updated: 2026-10-06 | 12 failing / 26 total
Port gHashTag/trinity:fpga/openxc7-synth/blink_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/blink #6730 Port gHashTag/trinity:fpga/openxc7-synth/blink_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/blink | Created: 2026-10-06 | Updated: 2026-10-06 | 3 failing / 26 total
Port scripts/ci/loop-tools-tracked.sh (Shell, 1 function) to specs/port/scripts/ci/loop-tools-tracked.t27 #6729 Port scripts/ci/loop-tools-tracked.sh (Shell, 1 function) to specs/port/scripts/ci/loop-tools-tracked.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 2 failing / 26 total
Port gHashTag/trinity:src/vibeec/p2p_module.zig (Zig, 4 functions) to specs/port/trinity/src/vibeec/p2p_module.t27 #6728 Port gHashTag/trinity:src/vibeec/p2p_module.zig (Zig, 4 functions) to specs/port/trinity/src/vibeec/p2p_module.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 2 failing / 26 total
Test the 1 untested function in specs/fpga/testbench/simulator_tb.t27 #6727 Test the 1 untested function in specs/fpga/testbench/simulator_tb.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 7 failing / 32 total
Implement the 1 empty function body in specs/tri/graph/graph_dfs.t27 #6726 Implement the 1 empty function body in specs/tri/graph/graph_dfs.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 2 failing / 26 total
Port bootstrap/src/bitnet_irq.rs (Rust, 3 functions) to specs/port/bootstrap/src/bitnet_irq.t27 #6725 Port bootstrap/src/bitnet_irq.rs (Rust, 3 functions) to specs/port/bootstrap/src/bitnet_irq.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 2 failing / 26 total
Port scripts/fpga/flash.sh (Shell, 8 functions) to specs/port/scripts/fpga/flash.t27 #6724 Port scripts/fpga/flash.sh (Shell, 8 functions) to specs/port/scripts/fpga/flash.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 1 failing / 26 total
t27b checked: test blocks for 7 specs in specs/crons (4 of 8) #6723 t27b checked: test blocks for 7 specs in specs/crons (4 of 8) | Created: 2026-10-06 | Updated: 2026-10-06 | 1 failing / 26 total
t27b checked: test blocks for 7 specs in specs/crons (5 of 8) #6722 t27b checked: test blocks for 7 specs in specs/crons (5 of 8) | Created: 2026-10-06 | Updated: 2026-10-06 | 1 failing / 26 total
t27b checked: test blocks for 7 specs in specs/crons (6 of 8) #6721 t27b checked: test blocks for 7 specs in specs/crons (6 of 8) | Created: 2026-10-06 | Updated: 2026-10-06 | 2 failing / 26 total
Port gHashTag/trinity:src/brain/weber_tuning.zig (Zig, 5 functions) to specs/port/trinity/src/brain/weber_tuning.t27 #6718 Port gHashTag/trinity:src/brain/weber_tuning.zig (Zig, 5 functions) to specs/port/trinity/src/brain/weber_tuning.t27 | Created: 2026-10-06 | Updated: 2026-10-06 | 1 failing / 26 total
feat(t27b): --check interpreter fuel per file, policy in check_budget.t27 (Closes #6664) #6695 feat(t27b): --check interpreter fuel per file, policy in check_budget.t27 (Closes #6664) | Created: 2026-10-06 | Updated: 2026-10-06 | 3 failing / 37 total
fix(fpga): elaboration ratchet green -- uart restored, adapter recorded, ternary_isa a named gap #6686 fix(fpga): elaboration ratchet green -- uart restored, adapter recorded, ternary_isa a named gap | Created: 2026-10-06 | Updated: 2026-10-06 | 8 failing / 31 total
fix(proofs): real Lean model for ar_ternary_logic, theorem = false; leave the ledger #6684 fix(proofs): real Lean model for ar_ternary_logic, theorem = false; leave the ledger | Created: 2026-10-06 | Updated: 2026-10-06 | 16 failing / 35 total
t27b checked: test blocks for 1 specs in specs/docs (1 of 1) #6623 t27b checked: test blocks for 1 specs in specs/docs (1 of 1) | Created: 2026-10-05 | Updated: 2026-10-05 | 1 failing / 26 total
t27b checked: test blocks for 1 specs in specs/tools/trinity/tri (1 of 1) #6622 t27b checked: test blocks for 1 specs in specs/tools/trinity/tri (1 of 1) | Created: 2026-10-05 | Updated: 2026-10-05 | 1 failing / 27 total
t27b checked: test blocks for 5 specs in specs/agents (4 of 4) #6620 t27b checked: test blocks for 5 specs in specs/agents (4 of 4) | Created: 2026-10-05 | Updated: 2026-10-05 | 2 failing / 26 total
feat(gen-ts): list skipped fns/tests in __NOT_EMITTED__; opt-in --fn lowers pure fn bodies (#6559) #6613 feat(gen-ts): list skipped fns/tests in NOT_EMITTED; opt-in --fn lowers pure fn bodies (#6559) | Created: 2026-10-05 | Updated: 2026-10-05 | 8 failing / 37 total
feat(t27c): every gen path runs typecheck first (Closes #6446) [needs owner label] #6577 feat(t27c): every gen path runs typecheck first (Closes #6446) [needs owner label] | Created: 2026-10-05 | Updated: 2026-10-05 | 7 failing / 37 total
bitwalk: --help and a missing file panic instead of printing usage or an error #6551 bitwalk: --help and a missing file panic instead of printing usage or an error | Created: 2026-10-05 | Updated: 2026-10-05 | 3 failing / 26 total
security: lefthook + gitleaks secret gate (pre-commit, pre-push, CI); remove OSF token #6433 security: lefthook + gitleaks secret gate (pre-commit, pre-push, CI); remove OSF token | Created: 2026-10-05 | Updated: 2026-10-05 | 2 failing / 24 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/agents/hermes/hermes-provider-map.ts (TypeScript, 2 funct #6399 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/agents/hermes/hermes-provider-map.ts (TypeScript, 2 funct | Created: 2026-10-05 | Updated: 2026-10-05 | 3 failing / 25 total
Port bootstrap/src/ternary/mod.rs (Rust, 3 functions) to specs/port/bootstrap/src/ternary/mod.t27 #6208 Port bootstrap/src/ternary/mod.rs (Rust, 3 functions) to specs/port/bootstrap/src/ternary/mod.t27 | Created: 2026-10-04 | Updated: 2026-10-04 | 5 failing / 25 total
Port tools/check_devhome_paths.py (Python, 6 functions) to specs/port/tools/check_devhome_paths.t27 #6206 Port tools/check_devhome_paths.py (Python, 6 functions) to specs/port/tools/check_devhome_paths.t27 | Created: 2026-10-04 | Updated: 2026-10-04 | 6 failing / 25 total
Port tools/c_error_classes.py (Python, 6 functions) to specs/port/tools/c_error_classes.t27 #6205 Port tools/c_error_classes.py (Python, 6 functions) to specs/port/tools/c_error_classes.t27 | Created: 2026-10-04 | Updated: 2026-10-04 | 5 failing / 25 total
fix(t27c): gen-c arithmetic traps where t27 traps, with no C undefined behaviour #6181 fix(t27c): gen-c arithmetic traps where t27 traps, with no C undefined behaviour | Created: 2026-10-04 | Updated: 2026-10-04 | 0 failing / 3 total
fix(xilinx7): bitwalk prints usage and clean errors instead of panicking (Closes #6039) #6073 fix(xilinx7): bitwalk prints usage and clean errors instead of panicking (Closes #6039) | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 25 total
self-host: give Gamma (agent C) a /self-host skill for epic #5980 #6057 self-host: give Gamma (agent C) a /self-host skill for epic #5980 | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 25 total
hooks: pre-commit trusts a PATH tri only if it has hooks pre-commit (#6009) #6011 hooks: pre-commit trusts a PATH tri only if it has hooks pre-commit (#6009) | Created: 2026-10-04 | Updated: 2026-10-04 | 0 failing / 25 total
ci: every check is a .t27 card -- schema, generator, three pilots (P1 of #5933) #5970 ci: every check is a .t27 card -- schema, generator, three pilots (P1 of #5933) | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 30 total
fpga: elaboration ratchet back to 176 -- ternary_isa (W459), uart (spec), adapter (NEW-clean) (Closes #5908) #5948 fpga: elaboration ratchet back to 176 -- ternary_isa (W459), uart (spec), adapter (NEW-clean) (Closes #5908) | Created: 2026-10-04 | Updated: 2026-10-06 | 1 failing / 46 total
CI: spec-guards and emit-bitexact restore master cargo caches; cancel superseded emit-bitexact runs (B25) #5924 CI: spec-guards and emit-bitexact restore master cargo caches; cancel superseded emit-bitexact runs (B25) | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 32 total
ring-096 and formats.t27 agree on f32 (Closes #5746) #5921 ring-096 and formats.t27 agree on f32 (Closes #5746) | Created: 2026-10-04 | Updated: 2026-10-06 | 1 failing / 56 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/queen-lane-credits.ts (TypeScript, 4 functions) #5778 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/queen-lane-credits.ts (TypeScript, 4 functions) | Created: 2026-10-03 | Updated: 2026-10-03 | 3 failing / 32 total
bees/merger/publisher: reviewer bee as a service, merger reads discounted checks, publisher heading passes check (Closes #5776) #5777 bees/merger/publisher: reviewer bee as a service, merger reads discounted checks, publisher heading passes check (Closes #5776) | Created: 2026-10-03 | Updated: 2026-10-04 | 0 failing / 3 total
fix(tri): gates preview asks the contexts the ruleset requires, parse-ratchet among them (Closes #5725) #5732 fix(tri): gates preview asks the contexts the ruleset requires, parse-ratchet among them (Closes #5725) | Created: 2026-10-03 | Updated: 2026-10-04 | 0 failing / 7 total
docs(igla): re-take the corpus figures on master, 1150 specs (Refs #5497) #5610 docs(igla): re-take the corpus figures on master, 1150 specs (Refs #5497) | Created: 2026-10-02 | Updated: 2026-10-02 | 1 failing / 34 total
The Queen's accept is the merge: dispatch.t27 says so, and its harness measures it #5452 The Queen's accept is the merge: dispatch.t27 says so, and its harness measures it | Created: 2026-10-01 | Updated: 2026-10-06 | 6 failing / 36 total
docs(tri): mark the Solana tri-mining program and depin.prove rewards superseded by mint-on-acceptance (Closes #5412) #5413 docs(tri): mark the Solana tri-mining program and depin.prove rewards superseded by mint-on-acceptance (Closes #5412) | Created: 2026-10-01 | Updated: 2026-10-02 | 6 failing / 32 total

Summary

Status	Count
Total Open PRs	50
PRs with Failing Checks	38
PRs with All Checks Green	12
READY	4
FAILING	38
PENDING	0
NO CHECKS YET	0

These columns do not partition: 4 + 38 + 0 + 0 = 42, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

⚠️ STALE -- sha256(compiler.rs)=3c78f3c7ffb7 != manifest seal=87e5cbd3ad94.
The committed NMSE numbers were certified against an older compiler.rs.
Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

Trinity Bee and others added 2 commits October 5, 2026 08:48

This was referenced Oct 6, 2026

feat(verified): run-level verdict rule (FR-004 of #6656, epic #6655) #6732

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Port fpga/vivado/matmul_serial_top.v (Verilog, 1 module) to specs/port/fpga/vivado/matmul_serial_top.t27 #6734

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Port fpga/verilog/ternary_mac_demo_top_v2.v (Verilog, 1 module) to specs/port/fpga/verilog/ternary_mac_demo_top_v2.t27 - #6735

Port fpga/verilog/ternary_mac_demo_top_v2.v (Verilog, 1 module) to specs/port/fpga/verilog/ternary_mac_demo_top_v2.t27#6735
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