fix(specs): the 8 specs the gen typecheck gate would refuse (Refs #6446) - #6566
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gft64..gft1024 declare their offsets in the storage word the formats catalog names (u64..u1024) instead of u32; ar/composition returns a switch instead of a Rust match; git/diff is rewritten in the status.t27 idiom with pure parsers under test; check_conflict_markers calls _git with its four parameters. 9 seals re-saved on the Railway lab; 7 typecheck ledger entries removed (84 -> 77). Lab: typecheck 1274/1274, RATCHET CLEAN, tri misread 0/0/0. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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…ain (Refs #6446) compiler/codegen/verilog/codegen.t27 calls mangle_verilog_name as a method; contrib/backend/zig/legacy/main_zig_handwritten.t27 sends its 14 formatted errors through printErrorFmt instead of the 1-parameter printError. Both typecheck and generate on the Railway lab; 3 seals re-saved there. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-10-05 17:23:33 UTC
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This was referenced Oct 5, 2026
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Refs #6446
On the Railway lab, the held gen typecheck gate (branch
claude/t27c-gen-typecheck-gate) stopped 8 corpus specs from generating. This PR fixes each one at the source, so the gate would cost nothing. The PR contains only .t27 specs, tool-written seals and ledger data, and prose. No hand-written non-t27 code.What changed
EXP_OFFSET/OFFSET_MAXdeclareu32for 12- to 187-digit values (#2925)formats_catalog.t27already names for the rung: u64, u128, u256, u512, u1024. The same change applies tois_finite's parameter. Tests pass under zig (2/2 each).matchinexecute_ar_component, with tuple-assigning arms (#5949)switchthat returns each arm's (result, steps) pairmatchblocks overOk/ErrofCommand::new("git")(#5949)git/status.t27idiom (run the command, check exit_code, parse), using pureparse_name_status/parse_numstat/summarizefunctions. The tests check those on literal git output._git(4 params) called with 7 argsLedger and seals
docs/reports/suite_expectations.json: 7typecheckentries removed (gft x5 for Ten constants declare a type they cannot fit; three of four backends emit them verbatim #2925, git/diff for t27c lowers a Rust match block to nothing, and typecheck accepts it #5949, check_conflict_markers for Fifteen ported specs do not parse and need their ports redone #5549), so 84 -> 77, andmax_entriesfollows. ar/composition keeps itsverilog-no-keyword-declentry, which is not a typecheck failure.blocked(undeclaredTrit/execute_commandin the generated test file), as the seals record.Lab measurement (master f2262f3 + this diff, master t27c)
The 9 gen-verilog failures are port specs with a local string array (
[N][]const u8). They fail the same way with or without the gate and stay ledgered under #5549.Two more refused specs outside
specs/(commit 726506c)Running the gate over the whole tree (
check_specs_generate.py,check_seal_coverage.py) turned up two more refused specs:compiler/codegen/verilog/codegen.t27called the methodmangle_verilog_name(self, name)withoutself.. The 3 call sites are nowself.mangle_verilog_name(..).contrib/backend/zig/legacy/main_zig_handwritten.t27made 14 calls that passed a format and args to the 1-parameterprintError. They now call the spec's ownprintErrorFmt.Both typecheck and generate on every backend on the lab. Their 3 seals were re-saved there (
verilog_codegen,verilog_verilog_codegen,legacy_main_zig_handwritten).Files
compiler/codegen/verilog/codegen.t27andcontrib/backend/zig/legacy/main_zig_handwritten.t27.trinity/seals/*.json(t27c seal --saveon the lab);suite_expectations.json(JSON filter dropping 7 entries)docs/now/2026-10-05-gate-refused-specs-6446.md🤖 Generated with Claude Code