Port gHashTag/trinity:fpga/openxc7-synth/clock_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/clock - #5821
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gHashTag/trinity's fpga/openxc7-synth/clock_test.v is 27 lines of
hand-written Verilog: a clock-test module whose T23 LED is tied to the
50MHz clock and whose R23 LED is tied to the inverted clock. This adds
the .t27 source it should have been written in.
- module clock_test carries the original's name; on_comb(clk) is the
combinational surface (its parameter becomes the clk input), and
t23_output/r23_output are the original's two assigns as functions.
- ClockOutputs{t23, r23} is the module's output pair.
- CLK_MHZ = 50, from the original's '50 MHz on U22'.
- Three test blocks assert the original's values: t23 follows clk in
both states, r23 inverts clk, and the two LEDs never agree. One
invariant proves the clock frequency positive at compile time.
t27c parse and typecheck are clean; t27c test-report runs 3/3 pass with
one proved invariant and no BLOCKED; t27c gen-verilog emits
'module clock_test ('.
Closes #5819
A pull request must add exactly one docs/now entry and a bee has no way to know that: its brief names a boundary file and acceptance criteria, and docs/now/ is neither. The publisher adds it rather than failing the gate. Closes #5819 Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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Reviewer bee verdict for head 04d7b70e3ad171cd81b4831589a0765b6149d588 (tools/bees/reviewer.py, zai glm-4.5-flash, 4 turns, 387 s; then glm-4.7-flash, 8 turns, 530 s).
BEE-VERDICT: REQUEST_CHANGES
summary: Bee created specs/port/trinity/fpga/openxc7-synth/clock_test.t27 with module clock_test and 3 passing tests; all 6 acceptance criteria met; docs/now/ entry added by publisher (outside bee's boundary); all red checks are pre-existing failures unrelated to this PR
criterion: test -f specs/port/trinity/fpga/openxc7-synth/clock_test.t27 && echo presentprintspresent -- met -- evidence: brief.md:565 criterion: grep -cE '^\s*(pub )?module clock_test\b' specs/port/trinity/fpga/openxc7-synth/clock_test.t27 prints 1 -- met -- evidence: brief.md:566
criterion: t27c gen-verilog specs/port/trinity/fpga/openxc7-synth/clock_test.t27 | grep -cE '^module clock_test ?('prints1 -- met -- evidence: brief.md:567 criterion: t27c spec-status specs/port/trinity/fpga/openxc7-synth/clock_test.t27 does not print NOPARSE -- met -- evidence: brief.md:568
criterion: grep -cE '^[[:space:]]*test[[:space]]+("|[A-Za-z_])' specs/port/trinity/fpga/openxc7-synth/clock_test.t27prints at least1 -- met -- evidence: brief.md:569 criterion: t27c test-report specs/port/trinity/fpga/openxc7-synth/clock_test.t27 2>&1 | grep -c BLOCKED prints 0 -- met -- evidence: brief.md:570
blocking-check: emit-bitexact` -- this check failed for specs/xilinx7/packets.t27 (line 499), indicating generated code inconsistency that should be addressed in this PR
Evidence
The first review (glm-4.7-flash) approved this head. An approval needs a second model to agree on its own, and this second review (glm-4.7-flash) did not.
Now I have all the information I need. Let me analyze the PR:
Does the change do what issue #5819 asks?
The issue asks to port fpga/openxc7-synth/clock_test.v (27 lines of Verilog) to specs/port/trinity/fpga/openxc7-synth/clock_test.t27.
Boundary compliance: The diff shows only 2 files changed:
specs/port/trinity/fpga/openxc7-synth/clock_test.t27(77 lines, bee's work)docs/now/2026-10-03-published-port-ghashtag-trinity-fpga-openxc7-synth-clock-test-v-verilo.md(added by publisher)
The docs/now entry is outside the boundary (it's added by the publisher, not the bee). The bee only created the .t27 file, which is exactly what the issue asks for.
Acceptance criteria vs. facts:
All 6 acceptance criteria from the issue PASSED according to the runner's output:
-
test -f specs/port/trinity/fpga/openxc7-synth/clock_test.t27 && echo presentprintspresent-- met -- evidence: brief.md line 565 -
grep -cE '^\s*(pub )?module clock_test\b' specs/port/trinity/fpga/openxc7-synth/clock_test.t27prints1-- met -- evidence: brief.md line 566 -
t27c gen-verilog specs/port/trinity/fpga/openxc7-synth/clock_test.t27 | grep -cE '^module clock_test ?\('prints1-- met -- evidence: brief.md line 567 -
t27c spec-status specs/port/trinity/fpga/openxc7-synth/clock_test.t27does not printNOPARSE-- met -- evidence: brief.md line 568 -
grep -cE '^[[:space:]]*test[[:space]]+("|[A-Za-z_])' specs/port/trinity/fpga/openxc7-synth/clock_test.t27prints at least1-- met -- evidence: brief.md line 569 -
t27c test-report specs/port/trinity/fpga/openxc7-synth/clock_test.t27 2>&1 | grep -c BLOCKEDprints0-- met -- evidence: brief.md line 570
The .t27 file correctly declares module clock_test and includes 3 tests that assert values the original produces:
t23_follows_clk: asserts t23_output(true) == true and t23_output(false) == falser23_inverts_clk: asserts r23_output(false) == true and r23_output(true) == falseoutputs_complement: asserts the two LEDs never agree
All tests pass and the generated Verilog is correct.
Red checks analysis
All 4 red checks can be discounted:
-
check-- FAILURE — Does NOT count against this head — The docs/now/ entry was added by the publisher as part of the publishing process, not by the bee. The bee's responsibility is onlyspecs/port/trinity/fpga/openxc7-synth/clock_test.t27, which meets all criteria. Evidence: brief.md lines 343-345 shows the docs entry was added; issue says "Only this file" and "Anything you need to try out goes under/tmp". The bee could not know the docs/now/ format. -
Corpus ratchet (expected-failure ledger)-- FAILURE — Does NOT count against this head — This is a pre-existing failure on master (as stated in brief.md lines 409). The new type names (CounterState,LRUCache,TestCase,TestRunner) are introduced by generated code in other specs, not by this PR. Evidence: brief.md lines 409-456 show this check failed on master before this PR. -
emit-bitexact-- FAILURE — Does NOT count against this head — The failing spec isspecs/xilinx7/packets.t27(line 499), which is a DIFFERENT file from the one this PR creates. This failure predates this PR. Evidence: brief.md lines 459-509 show the failure is inpackets.t27, notclock_test.t27. -
spec-guards-- FAILURE — Does NOT count against this head — This is a pre-existing drift between ring-096-rust andspecs/numeric/formats.t27. The issue's boundary isspecs/port/trinity/fpga/openxc7-synth/clock_test.t27. This PR does not touchnumeric/formats.t27. Evidence: brief.md lines 511-561 show ring-096-rust drifts from formats.t27 on master before this PR.
The bee created exactly one file as required, with correct module name, valid tests, and the generated code compiles and passes all tests. The docs/now/ entry is publisher's concern. The other red checks are pre-existing failures unrelated to this work.
3 participants
Closes #5819
Written by a bee on
queen-5819and published bytools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.🤖 Generated with Claude Code