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Port gHashTag/trinity:fpga/openxc7-synth/clock_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/clock - #5821

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Oct 4, 2026
Merged

Port gHashTag/trinity:fpga/openxc7-synth/clock_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/clock#5821
2 commits merged into
masterfrom
queen-5819

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Commits on Oct 3, 2026