bus-protocol

Here are 9 public repositories matching this topic...

FLASHICON / axi4-lite-register-mapped-peripheral

AXI4-Lite slave in SystemVerilog that exposes control, configuration, status and data registers to a bus master. It handles the five independent channels with proper VALID and READY handshakes, decodes addresses, and returns OKAY or error responses. A master model and protocol assertions verify it in Verilator.

asic verilog systemverilog gtkwave soc vlsi yosys digital-design verilator axi amba axi4 axi4-lite amba-axi rtl-design bus-protocol register-map slave-interface

Updated Nov 4, 2026

Ammar-Bin-Amir / AXI4

Star

RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle

verilog axi4 rtl-design bus-protocol axi4-lite-interface handshaking-algorithm

Updated Apr 7, 2024
Verilog

8bitgeek / libezbus

Star

EzBus is a true peer-to-peer token-bus protocol library intended to work on the RS-485 physical layer. Designed to run on resource constrained micro-controllers.

library microcontroller peer-to-peer socket-io rs-485 bus-protocol

Updated Mar 12, 2021
C

thaserge-primary / AC-fujitsu-General-EZ-0001HSEFR-integration

Star

Reverse-engineered Fujitsu FGL Type A wired bus protocol — for older Fujitsu/General air conditioners (2000-2010 era), wired remotes (EZ-0001HSEFR and similar). Full spec + Python tools.

home-automation iot esp32 reverse-engineering smart-home general hvac sigrok homeassistant loxone fujitsu air-conditioner bus-protocol protocol-spec fgl-bus

Updated May 10, 2026
Python

Nischal-Agrawal / Bustalk-Uart

Star

APB-controlled UART IP with memory-mapped registers, designed in Verilog and verified using simulation.

simulation verilog uart hardware-designs icarus-verilog gtkwave digital-design apb ip-core rtl-design bus-protocol

Updated Jan 25, 2026
Verilog

shreekanthkapparagaon / parameterized-apb3-slave

Star

Parameterized AMBA APB3 Slave Peripheral in Verilog with configurable register bank, reusable APB Master BFM, and self-checking verification environment.

asic fpga verification rtl verilog gtkwave vlsi iverilog digital-design apb rtl-design bus-protocol apb3 parameterized-design

Updated Jul 5, 2026
Verilog

raviranjan-vlsi / AMBA-AHB-Master-Slave-Interface-

Star

Verilog implementation of AMBA AHB Master and Slave with FSM control, FIFO integration, burst transfer (INCR4), and waveform-based protocol verification.

rtl verilog vivado soc vlsi digital-design ahb verilog-project vlsi-project rtl-design bus-protocol amba-project rtl-verification amba-ahb ahb-master ahb-slave

Updated May 8, 2026
Verilog

mohamed-abdulraziq / Parameterized-APB-Interconnect

Star

Parameterized single-master, multi-slave AMBA APB interconnect in SystemVerilog, featuring an IDLE/SETUP/ACCESS bridge, configurable RAM slaves, byte strobes, protection and address error handling, and self-checking verification.

fpga vivado systemverilog memory-mapped interconnect amba apb functional-verification rtl-design bus-protocol parameterized-design self-checking-testbench

Updated Nov 2, 2026
SystemVerilog

isaqueveron / Emulador-Eolico-Python-beta

Star

Este repositório contém os códigos, parâmetros e resultados de um ensaio de emulação de turbina eólica de eixo horizontal. O sistema utiliza um motor elétrico para mimetizar o comportamento dinâmico de uma turbina real sob perfis de vento variáveis.

simulation emulation wind-energy digital-twin process-control bus-protocol rs232-communication

Updated May 18, 2026
Python

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