rtl-verification

Open-source, license-free MCP server for RTL waveform debug: FST waveform + SystemVerilog netlist analysis, 27 tools including pre-simulation static analysis.

UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

5-Stage Pipelined RISC-V CPU utilizing the RV32I ISA, featuring dynamic branch prediction. Designed, verified, performance tested, and ASIC-flowed

EVPIX-RV32: 5-Stage Custom RISC-V SoC with Integrated IPU and TinyML Support for Real-Time Edge-Vision AI Acceleration: RTL-to-GDSII Design, Verification, Basys-3 Artix-7 FPGA Prototyping and SkyWater 130-nm CMOS ASIC was implementation

UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed QuestaSim regression debugging.

Single-cycle RISC-V CPU utilizing the RV32I ISA. Designed, verified and ASIC-flowed

A Verilog-based five-stage pipelined processor with complete hazard handling (stalling, forwarding) and modular RTL design.

Runnable AXI4-Lite master/slave RTL verification lab with UVM regressions, reference models, SVA and QuestaSim scripts.

The RTL implementation of a 8-bit pipelined signed integer multiplication module with some optimization techniques and testbench.

This repository contain all the necessary files to verify PISO Universal Register

AXI4 Memory Controller UVM Verification Environment with real Siemens Questa seed-1 simulation logs, scoreboard checks, functional coverage summaries, and documented burst-read debug fix.

RTL 验证自动管道：Humanize RLCR 循环驱动 Claude 写/改 RTL，UCAgent 作为客观验证门控（RTL verification autopilot: RLCR loop + UCAgent gate）

Configurable Multi-Mode SPI Master RTL design in SystemVerilog with support for all 4 SPI modes, MSB/LSB-first transmission, automated functional verification, Questa simulation, and Quartus synthesis analysis.

RustDV-based RTL verification environment for a parameterized synchronous FIFO using directed testing, deterministic randomized regression, functional coverage, corner-case testing, stress testing, scoreboard checking, VPI simulation, and GTKWave waveform analysis.

SystemVerilog and UVM RTL verification projects for UART, SPI, I2C and FPGA.

ETC10123 laboratory portfolio: SPI Master RTL, synthesis, Formality, ICC2 physical design, weekly labs, and release-backed reports.

RustDV-based RTL verification environment for a 4-bit TinyALU using directed testing, deterministic randomized regression, functional coverage, corner-case testing, scoreboard checking, VPI simulation, and GTKWave waveform analysis.

C-DAC Final Project | RISC-V RV32I Subset Design and Verification with UVM

RTL design of Pipelined Heap component