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FROMLIST: PCI: qcom-ep: Add PCIe Endpoint support for Monaco #1940

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fb3d57e
FROMLIST: dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add qcs8300 1…
krishnachaitanya-linux Sep 21, 2026
d0d24fa
FROMLIST: dt-bindings: PCI: qcom-ep: Add QCS8300 compatible
krishnachaitanya-linux Sep 21, 2026
8a1f3f1
FROMLIST: phy: qcom: qmp-pcie: Add endpoint PHY configuration for QCS…
krishnachaitanya-linux Sep 21, 2026
9995d9f
FROMLIST: PCI: qcom-ep: Set initial interconnect bandwidth before ena…
krishnachaitanya-linux Sep 21, 2026
68d122e
FROMLIST: arm64: qcom: monaco: Fix pcie1_phy compatible to list qcs83…
krishnachaitanya-linux Sep 21, 2026
20f8ccf
FROMLIST: arm64: qcom: monaco: Add PCIe Endpoint nodes
krishnachaitanya-linux Sep 21, 2026
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5 changes: 5 additions & 0 deletions Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,15 @@ properties:
compatible:
oneOf:
- enum:
- qcom,qcs8300-pcie-ep
- qcom,sa8775p-pcie-ep
- qcom,sar2130p-pcie-ep
- qcom,sdx55-pcie-ep
- qcom,sm8450-pcie-ep
- items:
- enum:
- qcom,qcs8300-pcie-ep
- const: qcom,sa8775p-pcie-ep
- items:
- const: qcom,sdx65-pcie-ep
- const: qcom,sdx55-pcie-ep
Expand Down
87 changes: 46 additions & 41 deletions Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -15,47 +15,52 @@ description:

properties:
compatible:
enum:
- qcom,eliza-qmp-gen3x1-pcie-phy
- qcom,eliza-qmp-gen3x2-pcie-phy
- qcom,glymur-qmp-gen4x2-pcie-phy
- qcom,glymur-qmp-gen5x4-pcie-phy
- qcom,hawi-qmp-gen3x2-pcie-phy
- qcom,hawi-qmp-gen4x1-pcie-phy
- qcom,kaanapali-qmp-gen3x2-pcie-phy
- qcom,qcs615-qmp-gen3x1-pcie-phy
- qcom,qcs8300-qmp-gen4x2-pcie-phy
- qcom,sa8775p-qmp-gen4x2-pcie-phy
- qcom,sa8775p-qmp-gen4x4-pcie-phy
- qcom,sar2130p-qmp-gen3x2-pcie-phy
- qcom,sc8180x-qmp-pcie-phy
- qcom,sc8280xp-qmp-gen3x1-pcie-phy
- qcom,sc8280xp-qmp-gen3x2-pcie-phy
- qcom,sc8280xp-qmp-gen3x4-pcie-phy
- qcom,sdm845-qhp-pcie-phy
- qcom,sdm845-qmp-pcie-phy
- qcom,sdx55-qmp-pcie-phy
- qcom,sdx65-qmp-gen4x2-pcie-phy
- qcom,sm8150-qmp-gen3x1-pcie-phy
- qcom,sm8150-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-gen3x1-pcie-phy
- qcom,sm8250-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-modem-pcie-phy
- qcom,sm8350-qmp-gen3x1-pcie-phy
- qcom,sm8350-qmp-gen3x2-pcie-phy
- qcom,sm8450-qmp-gen3x1-pcie-phy
- qcom,sm8450-qmp-gen4x2-pcie-phy
- qcom,sm8475-qmp-gen3x1-pcie-phy
- qcom,sm8550-qmp-gen3x2-pcie-phy
- qcom,sm8550-qmp-gen4x2-pcie-phy
- qcom,sm8650-qmp-gen3x2-pcie-phy
- qcom,sm8650-qmp-gen4x2-pcie-phy
- qcom,sm8750-qmp-gen3x2-pcie-phy
- qcom,x1e80100-qmp-gen3x2-pcie-phy
- qcom,x1e80100-qmp-gen4x2-pcie-phy
- qcom,x1e80100-qmp-gen4x4-pcie-phy
- qcom,x1e80100-qmp-gen4x8-pcie-phy
- qcom,x1p42100-qmp-gen4x4-pcie-phy
oneOf:
- items:
- enum:
- qcom,qcs8300-qmp-gen4x4-pcie-phy
- const: qcom,sa8775p-qmp-gen4x4-pcie-phy
- enum:
- qcom,eliza-qmp-gen3x1-pcie-phy
- qcom,eliza-qmp-gen3x2-pcie-phy
- qcom,glymur-qmp-gen4x2-pcie-phy
- qcom,glymur-qmp-gen5x4-pcie-phy
- qcom,hawi-qmp-gen3x2-pcie-phy
- qcom,hawi-qmp-gen4x1-pcie-phy
- qcom,kaanapali-qmp-gen3x2-pcie-phy
- qcom,qcs615-qmp-gen3x1-pcie-phy
- qcom,qcs8300-qmp-gen4x2-pcie-phy
- qcom,sa8775p-qmp-gen4x2-pcie-phy
- qcom,sa8775p-qmp-gen4x4-pcie-phy
- qcom,sar2130p-qmp-gen3x2-pcie-phy
- qcom,sc8180x-qmp-pcie-phy
- qcom,sc8280xp-qmp-gen3x1-pcie-phy
- qcom,sc8280xp-qmp-gen3x2-pcie-phy
- qcom,sc8280xp-qmp-gen3x4-pcie-phy
- qcom,sdm845-qhp-pcie-phy
- qcom,sdm845-qmp-pcie-phy
- qcom,sdx55-qmp-pcie-phy
- qcom,sdx65-qmp-gen4x2-pcie-phy
- qcom,sm8150-qmp-gen3x1-pcie-phy
- qcom,sm8150-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-gen3x1-pcie-phy
- qcom,sm8250-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-modem-pcie-phy
- qcom,sm8350-qmp-gen3x1-pcie-phy
- qcom,sm8350-qmp-gen3x2-pcie-phy
- qcom,sm8450-qmp-gen3x1-pcie-phy
- qcom,sm8450-qmp-gen4x2-pcie-phy
- qcom,sm8475-qmp-gen3x1-pcie-phy
- qcom,sm8550-qmp-gen3x2-pcie-phy
- qcom,sm8550-qmp-gen4x2-pcie-phy
- qcom,sm8650-qmp-gen3x2-pcie-phy
- qcom,sm8650-qmp-gen4x2-pcie-phy
- qcom,sm8750-qmp-gen3x2-pcie-phy
- qcom,x1e80100-qmp-gen3x2-pcie-phy
- qcom,x1e80100-qmp-gen4x2-pcie-phy
- qcom,x1e80100-qmp-gen4x4-pcie-phy
- qcom,x1e80100-qmp-gen4x8-pcie-phy
- qcom,x1p42100-qmp-gen4x4-pcie-phy

reg:
minItems: 1
Expand Down
147 changes: 146 additions & 1 deletion arch/arm64/boot/dts/qcom/monaco.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -2405,6 +2405,55 @@
};
};

pcie0_ep: pcie-ep@1c00000 {
compatible = "qcom,qcs8300-pcie-ep", "qcom,sa8775p-pcie-ep";
reg = <0x0 0x01c00000 0x0 0x3000>,
<0x0 0x40000000 0x0 0xf20>,
<0x0 0x40000f20 0x0 0xa8>,
<0x0 0x40001000 0x0 0x4000>,
<0x0 0x40200000 0x0 0x1fe00000>,
<0x0 0x01c03000 0x0 0x1000>,
<0x0 0x40005000 0x0 0x2000>;
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
"mmio", "dma";

clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
clock-names = "aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a";

interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global", "doorbell", "dma";

interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "pcie-mem", "cpu-pcie";

dma-coherent;
iommus = <&pcie_smmu 0x0000 0x7f>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "core";
power-domains = <&gcc GCC_PCIE_0_GDSC>;
phys = <&pcie0_phy>;
phy-names = "pciephy";
pinctrl-0 = <&pcie0_ep_default_state>;
pinctrl-names = "default";
num-lanes = <2>;
linux,pci-domain = <0>;

status = "disabled";
};

pcie0_phy: phy@1c04000 {
compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy";
reg = <0x0 0x01c04000 0x0 0x2000>;
Expand Down Expand Up @@ -2596,8 +2645,58 @@
};
};

pcie1_ep: pcie-ep@1c10000 {
compatible = "qcom,qcs8300-pcie-ep", "qcom,sa8775p-pcie-ep";
reg = <0x0 0x01c10000 0x0 0x3000>,
<0x0 0x60000000 0x0 0xf20>,
<0x0 0x60000f20 0x0 0xa8>,
<0x0 0x60001000 0x0 0x4000>,
<0x0 0x60200000 0x0 0x1fe00000>,
<0x0 0x01c13000 0x0 0x1000>,
<0x0 0x60005000 0x0 0x2000>;
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
"mmio", "dma";

clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
clock-names = "aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a";

interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global", "doorbell", "dma";

interconnects = <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "pcie-mem", "cpu-pcie";

dma-coherent;
iommus = <&pcie_smmu 0x0080 0x7f>;
resets = <&gcc GCC_PCIE_1_BCR>;
reset-names = "core";
power-domains = <&gcc GCC_PCIE_1_GDSC>;
phys = <&pcie1_phy>;
phy-names = "pciephy";
pinctrl-0 = <&pcie1_ep_default_state>;
pinctrl-names = "default";
num-lanes = <4>;
linux,pci-domain = <1>;

status = "disabled";
};

pcie1_phy: phy@1c14000 {
compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
compatible = "qcom,qcs8300-qmp-gen4x4-pcie-phy",
"qcom,sa8775p-qmp-gen4x4-pcie-phy";
reg = <0x0 0x01c14000 0x0 0x4000>;

clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
Expand Down Expand Up @@ -6224,6 +6323,52 @@
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;

pcie0_ep_default_state: pcie0-ep-default-state {
wake-pins {
pins = "gpio0";
function = "gpio";
drive-strength = <2>;
output-low;
};

clkreq-pins {
pins = "gpio1";
function = "pcie0_clkreq";
drive-strength = <2>;
bias-pull-up;
};

perst-pins {
pins = "gpio2";
function = "gpio";
input-enable;
bias-pull-up;
};
};

pcie1_ep_default_state: pcie1-ep-default-state {
wake-pins {
pins = "gpio21";
function = "gpio";
drive-strength = <2>;
output-low;
};

clkreq-pins {
pins = "gpio22";
function = "pcie1_clkreq";
drive-strength = <2>;
bias-pull-up;
};

perst-pins {
pins = "gpio23";
function = "gpio";
input-enable;
bias-pull-up;
};
};

cam0_default: cam0-default-state {
pins = "gpio67";
function = "cam_mclk";
Expand Down
34 changes: 17 additions & 17 deletions drivers/pci/controller/dwc/pcie-qcom-ep.c
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -331,9 +331,23 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
struct dw_pcie *pci = &pcie_ep->pci;
int ret;

/*
* Some Qualcomm platforms require interconnect bandwidth constraints
* to be set before enabling interconnect clocks.
*
* Set an initial peak bandwidth corresponding to single-lane Gen 1
* for the pcie-mem path.
*/
ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
if (ret) {
dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
ret);
return ret;
}

ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks);
if (ret)
return ret;
goto err_disable_icc;

ret = qcom_pcie_ep_core_reset(pcie_ep);
if (ret)
Expand All @@ -351,28 +365,14 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
if (ret)
goto err_phy_exit;

/*
* Some Qualcomm platforms require interconnect bandwidth constraints
* to be set before enabling interconnect clocks.
*
* Set an initial peak bandwidth corresponding to single-lane Gen 1
* for the pcie-mem path.
*/
ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
if (ret) {
dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
ret);
goto err_phy_off;
}

return 0;

err_phy_off:
phy_power_off(pcie_ep->phy);
err_phy_exit:
phy_exit(pcie_ep->phy);
err_disable_clk:
clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
err_disable_icc:
icc_set_bw(pcie_ep->icc_mem, 0, 0);

return ret;
}
Expand Down
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