FROMLIST: PCI: qcom-ep: Add PCIe Endpoint support for Monaco - #1940
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…6 GT/s PHY The QCS8300 16 GT/s x4 QMP PCIe PHY was previously described using only the qcom,sa8775p-qmp-gen4x4-pcie-phy compatible, since no QCS8300-specific compatible existed for this PHY. This was a mistake, as it left the PHY undocumented as QCS8300 hardware and indistinguishable from SA8775P in the binding. Correct this by documenting a dedicated "qcom,qcs8300-qmp-gen4x4-pcie-phy" compatible, with "qcom,sa8775p-qmp-gen4x4-pcie-phy" listed as its fallback compatible. Link: https://lore.kernel.org/r/20260921-monaco_ep-v1-1-63c5282fb0db@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
The QCS8300 PCIe Endpoint controller is compatible with the SA8775P PCIe Endpoint controller and uses the same programming model. Document the QCS8300 compatible string and its fallback to the SA8775P compatible. Link: https://lore.kernel.org/r/20260921-monaco_ep-v1-2-63c5282fb0db@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
…8300 Monaco supports PCIe Endpoint mode on both PCIe controllers. Reuse the existing SA8775P Endpoint PHY programming for the 16 GT/s x2 PHY and add a new 16 GT/s x4 Endpoint PHY configuration with the required RX tuning parameters. This allows both Monaco PCIe controllers to operate reliably in Endpoint mode. Link: https://lore.kernel.org/r/20260921-monaco_ep-v1-3-63c5282fb0db@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
…bling clocks Some Qualcomm platforms require the interconnect bandwidth constraints to be set before enabling the interconnect clocks, otherwise some clocks get stuck in the off state. Move the icc_set_bw() call before clk_bulk_prepare_enable() so the bandwidth vote is in place first. Link: https://lore.kernel.org/r/20260921-monaco_ep-v1-4-63c5282fb0db@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
…00 first The existing pcie1_phy node only listed qcom,sa8775p-qmp-gen4x4-pcie-phy compatible, since no QCS8300-specific compatible was documented for this PHY at the time. Now that qcom,qcs8300-qmp-gen4x4-pcie-phy is documented, list it first with qcom,sa8775p-qmp-gen4x4-pcie-phy as its fallback, matching the order used by the pcie0_ep and pcie1_ep nodes. Link: https://lore.kernel.org/r/20260921-monaco_ep-v1-5-63c5282fb0db@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Monaco has two PCIe controllers that can operate in Endpoint mode. Describe the Endpoint nodes for both controllers, including their register regions, clocks, interrupts, interconnects, IOMMU mappings, resets, power domains, and PHY connections etc. Link: https://lore.kernel.org/r/20260921-monaco_ep-v1-6-63c5282fb0db@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
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Dev Completion validation failed CR: 4694550 The change task for this CR could not be moved to Dev Complete because of the error above. Please resolve the issue in Orbit and re-run the failed Orbit check. |
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September 30, 2026 02:22
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Add PCIe Endpoint support for Monaco (QCS8300) — dt-bindings, PHY configuration, driver fix, and DTS nodes.
Change 1: dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add qcs8300 16 GT/s PHY
Document a dedicated "qcom,qcs8300-qmp-gen4x4-pcie-phy" compatible with "qcom,sa8775p-qmp-gen4x4-pcie-phy" as its fallback.
Change 2: dt-bindings: PCI: qcom-ep: Add QCS8300 compatible
Document the QCS8300 PCIe Endpoint compatible string and its fallback to SA8775P.
Change 3: phy: qcom: qmp-pcie: Add endpoint PHY configuration for QCS8300
Add 16 GT/s x4 Endpoint PHY configuration with required RX tuning parameters for Monaco.
Change 4: PCI: qcom-ep: Set initial interconnect bandwidth before enabling clocks
Move icc_set_bw() before clk_bulk_prepare_enable() to avoid clocks getting stuck in the off state.
Change 5: arm64: qcom: monaco: Fix pcie1_phy compatible to list qcs8300 first
List qcom,qcs8300-qmp-gen4x4-pcie-phy first with sa8775p as fallback.
Change 6: arm64: qcom: monaco: Add PCIe Endpoint nodes
Add pcie0_ep and pcie1_ep nodes for both Monaco PCIe controllers operating in Endpoint mode.
Link: https://lore.kernel.org/all/20260921-monaco_ep-v1-0-63c5282fb0db@oss.qualcomm.com/
CRs-Fixed:4694550