Multi-Scalar Configuration

Bender.yml

@@ -42,6 +42,9 @@ sources:
   - hardware/generated/floo_cachepool_noc_pkg.sv
   - hardware/src/cachepool_pkg.sv
   - hardware/src/cachepool_cc.sv
+  - hardware/src/cachepool_spatz_lock.sv
+  - hardware/src/acc_mux.sv
+  - hardware/src/cachepool_cc_dual.sv
   # Barrier
   - hardware/src/cachepool_tile_barrier.sv
   - hardware/src/cachepool_cluster_barrier.sv

Makefile

@@ -190,12 +190,12 @@ $(info FLOO_DIR: $(FLOO_DIR))
 # Generates the sources for FlooNoC
 .PHONY: update-floonoc install-floogen clean-floonoc
 install-floogen:
-	pip install -e $(FLOO_DIR) --quiet
+	$(PYTHON) -m pip install -e $(FLOO_DIR) --quiet
 
 update-floonoc: $(FLOO_NOC)
 $(FLOO_NOC): $(FLOO_CFG)
 	mkdir -p $(FLOO_GEN_OUTDIR)
-	PATH="$(HOME)/.local/bin:$(PATH)" floogen pkg -c $(FLOO_CFG) -o $(FLOO_GEN_OUTDIR) --no-format
+	floogen pkg -c $(FLOO_CFG) -o $(FLOO_GEN_OUTDIR) --no-format
 
 clean-floonoc:
 	rm -f $(FLOO_NOC)
@@ -298,6 +298,10 @@ VLOG_DEFS += -DSPATZ_NUM_FPU=$(spatz_num_fpu)
 VLOG_DEFS += -DSPATZ_NUM_IPU=$(spatz_num_ipu)
 VLOG_DEFS += -DSPATZ_MAX_TRANS=$(spatz_max_trans)
 VLOG_DEFS += -DSNITCH_MAX_TRANS=$(snitch_max_trans)
+VLOG_DEFS += -DNUM_SCALAR_PER_CC=$(num_scalar_per_core)
+ifeq ($(num_scalar_per_core),2)
+VLOG_DEFS += -DCACHEPOOL_DUAL_CC
+endif
 VLOG_DEFS += -DLG_PORT_PER_CORE=$(num_lg_ports_per_core)
 VLOG_DEFS += -DRG_PORT_PER_CORE=$(num_rg_ports_per_core)
 VLOG_DEFS += -DNOC_PORT_PER_TILE=$(num_noc_ports_per_tile)
@@ -384,23 +388,32 @@ $(BANDWIDTH_DATA): $(TESTS_DIR)/bandwidth/script/data.json \
 .PHONY: gen-data
 gen-data: $(ALL_GEN_DATA)
 
+# Clean targets, used to delete generated files
 .PHONY: clean.data
 clean.data:
 	rm -f $(ALL_GEN_DATA)
 
 .PHONY: clean.sw
-clean.sw:
+clean.sw: clean.data
 	rm -rf ${SOFTWARE_DIR}/build
 
-.PHONY: clean
-clean: clean.sw clean.vsim clean.data
+.PHONY: clean.generate
+clean.generate:
 	rm -rf $(HJSON_OUT) $(BOOTROM_DIR)/bootdata.cc \
 	                    $(BOOTROM_DIR)/bootdata_bootrom.cc \
 	                    $(BOOTROM_DIR)/bootrom.sv \
 	                    $(BOOTROM_DIR)/bootrom.dump \
 	                    $(BOOTROM_DIR)/bootrom.elf \
+	                    $(CACHEPOOL_DIR)/wlf* \
+	                    $(CACHEPOOL_DIR)/noc_profiling/* \
 	                    $(SNRT_BOOTINFO_H)
 
+.PHONY: clean.hw
+clean.hw: clean.vsim clean.generate
+
+.PHONY: clean
+clean: clean.hw clean.sw
+
 # Common CMake flags shared by sw and vsim targets.
 # vsim appends -DSNITCH_SIMULATOR to point tests at the compiled binary.
 SW_CMAKE_FLAGS = \
@@ -411,7 +424,8 @@ SW_CMAKE_FLAGS = \
   -DLLVM_PATH=${LLVM_INSTALL_DIR} \
   -DGCC_PATH=${GCC_INSTALL_DIR} \
   -DPYTHON=${PYTHON} \
-  -DBUILD_TESTS=ON
+  -DBUILD_TESTS=ON \
+  -DNUM_SCALAR_PER_CORE=$(num_scalar_per_core)
 
 .PHONY: sw
 sw: generate bootrom gen-data
@@ -428,8 +442,11 @@ vsim: generate bootrom dpi ${SIMBIN_DIR}/cachepool_cluster.vsim
 ############
 
 # Just a shortcut to build everything
+.PHONY: hw
+hw: generate bootrom vsim
+
 .PHONY: all
-all: generate bootrom vsim sw
+all: hw sw
 
 ########
 # Lint #
@@ -463,9 +480,7 @@ avg-log:
 # NoC traffic visualization frontend (fork of https://github.com/ueqri/vis4mesh
 # with CachePool-specific fixes/features). Consumes the Vis4Mesh dataset
 # directories produced by util/scripts/noc_profiling_to_vis4mesh.py from
-# hardware/tb/cachepool_noc_profiling.sv's per-cycle NoC logs. Fetched as a
-# plain pinned clone (same pattern as toolchain.mk's riscv-gnu-toolchain/
-# llvm-project targets), not a git submodule.
+# hardware/tb/cachepool_noc_profiling.sv's per-cycle NoC logs.
 NPM             ?= npm
 VIS4MESH_DIR    ?= ${CACHEPOOL_DIR}/util/vis4mesh
 VIS4MESH_REPO   ?= https://github.com/DiyouS/vis4mesh.git
@@ -531,13 +546,18 @@ help:
 	@echo "SW Build:"
 	@echo ""
 	@echo "*sw*:             build software (generate + bootrom + cmake); overwrites previous build"
-	@echo "*clean.sw*:       remove the software build directory"
+	@echo "*clean.sw*:       remove the software build directory (also runs clean.data)"
 	@echo ""
 	@echo "Simulation:"
 	@echo ""
 	@echo "*vsim*:           build hardware for QuestaSim simulation (use 'sw' to build software separately)"
+	@echo "*hw*:             shortcut for generate + bootrom + vsim"
+	@echo "*all*:            shortcut for hw + sw"
 	@echo "*clean.vsim*:     remove the hardware simulation build [from sim/sim.mk]"
-	@echo "*clean*:          remove SW build, vsim build, and all generated HW files"
+	@echo "*clean.data*:     remove generated data files (gen-data outputs)"
+	@echo "*clean.generate*: remove generated HJSON/bootrom/wlf/noc_profiling files [from 'generate'/'bootrom']"
+	@echo "*clean.hw*:       clean.vsim + clean.generate"
+	@echo "*clean*:          clean.hw + clean.sw (remove SW build, vsim build, and all generated HW files)"
 	@echo ""
 	@echo "Lint:"
 	@echo ""

README.md

@@ -111,6 +111,8 @@ make vsim config=cachepool_fpu_4g
 
 Set `DEBUG=0` to disable `+acc` waveform visibility and speed up simulation (used by CI); default is `DEBUG=1`.
 
+`make hw` is a shortcut for `generate bootrom vsim`; `make all` is a shortcut for `hw sw` (build everything).
+
 #### Run the Simulation
 
 The wrapper script launches the simulation (GUI or CLI) and expects a software ELF path as argument:
@@ -204,9 +206,12 @@ Configuration names encode the number of groups and whether the FPU is enabled:
 | `cachepool_fpu_4g` | 4 | 2×2 | Yes | 4 | 4 | 64 |
 | `cachepool_fpu_16g` | 16 | 4×4 | Yes | 4 | 4 | 256 |
 | `cachepool_fpu_16g_tiny` | 16 | 4×4 | Yes | 2 | 2 | 64 |
+| `cachepool_dual_4g` | 4 | 2×2 | No (IPU only) | 4 | 4 | 64 CCs / 128 harts |
 
 `cachepool_fpu_16g_tiny` shrinks tiles/group and cores/tile for a faster-to-build, faster-to-simulate smoke test of the full 16-group mesh topology.
 
+`cachepool_dual_4g` sets `num_scalar_per_core=2`: each Core Complex holds 2 Snitch scalar harts sharing 1 Spatz unit via a hardware ownership lock, so "Cores" (Core Complex slots) and hart count diverge — 64 CCs, 128 harts total. Software runtime support for the shared-Spatz lock is still in progress (see `note.md`).
+
 The Spatz cluster consumes **`config/cachepool.hjson`**, which is **generated** from:
 - `config/cachepool.hjson.tmpl` (skeleton with comments)
 - `config/config.mk` (source of truth)
@@ -408,7 +413,7 @@ make lint config=cachepool_fpu_4g
 - If you change cacheline width, `AXI_USER_WIDTH` is derived (supported widths: 128→19, 256→18, 512→17). Unsupported widths error out at generation time.
 - `make generate` regenerates the FlooNoC package automatically; only run `make update-floonoc` standalone if you're iterating on a `config/floonoc_*.yml` topology file without a full generate.
 - `make sw` and `make vsim` are decoupled (hw/sw build independently); rebuild whichever side you changed.
-- Use `make clean` when switching configs to prevent stale build artifacts.
+- Use `make clean` when switching configs to prevent stale build artifacts; `clean.sw`/`clean.hw` (or their finer-grained parts `clean.data`/`clean.generate`/`clean.vsim`) clean only one side if you don't need a full rebuild.
 - Runtime functions `snrt_tile_id()` and `snrt_num_tiles()` are available to query tile topology from software.
 - Changing the partition mode or boundary address while the cache holds valid data requires a flush (`l1d_cluster_flush()` or the appropriate cluster-wide partition flush) before reconfiguring.
 - Set `DEBUG=0` to disable `+acc` and speed up simulation (used by CI); default is `DEBUG=1` for waveform visibility.

config/cachepool_dual_4g.mk

@@ -0,0 +1,117 @@
+# Copyright 2026 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Author: Diyou Shen, ETH Zurich
+
+#########################
+##  CachePool Cluster  ##
+#########################
+
+# Number of groups
+num_groups ?= 4
+
+# 2×2 mesh
+num_groups_x ?= 2
+
+# Number of tiles
+num_tiles_per_group ?= 4
+
+# Number of Core Complex slots (each holding num_scalar_per_core harts)
+num_cores_per_tile  ?= 4
+
+# Core datawidth
+data_width ?= 32
+
+# Core addrwidth
+addr_width ?= 32
+
+num_lg_ports_per_core ?= 2
+
+num_rg_ports_per_core ?= 1
+
+num_noc_ports_per_tile ?= 4
+
+
+######################
+##  CachePool Tile  ##
+######################
+
+##### L1 Data Cache #####
+
+# L1 data cacheline width (in Bit)
+l1d_cacheline_width ?= 512
+
+# L1 data cache banking factor (how many banks per core?)
+l1d_bank_factor ?= 1
+
+# L1 coalecsing window
+l1d_coal_window ?= 2
+
+# L1 data cache number of ways per
+l1d_num_way ?= 4
+
+# L1 data cache size per tile (KiB)
+l1d_tile_size ?= 256
+
+# L1 data cache tag width (TODO: should be calcualted)
+l1d_tag_data_width ?= 92
+
+# Use folded (skewed) data banks
+l1d_use_folded ?= 1
+
+# Fold-way group size for skewed folded banks (0 = auto: min(4, ways))
+l1d_fold_way_group ?= 0
+
+# Use hash-based way selection (required by l1d_use_folded / l1d_use_fwd_buf)
+l1d_use_hash_way ?= 1
+
+# Enable the SRAM forwarding buffer (requires l1d_use_hash_way)
+l1d_use_fwd_buf ?= 1
+
+####################
+##  CachePool CC  ##
+####################
+# Spatz fpu support?
+spatz_fpu_en ?= 0
+
+# Spatz number of FPU
+spatz_num_fpu ?= 0
+
+# Spatz number of IPU
+spatz_num_ipu ?= 4
+
+# Spatz max outstanding transactions
+spatz_max_trans ?= 32
+
+# Snitch/FPU max outstanding transactions
+snitch_max_trans ?= 16
+
+# 2 Snitch scalar harts sharing one Spatz per Core Complex
+num_scalar_per_core ?= 2
+
+
+#####################
+##  L2 Main Memory ##
+#####################
+# DRAM type (selects DRAMSys config and sets default refill_data_width)
+dram_type ?= HBM2
+
+# L2 number of channels
+l2_channel ?= 4
+
+# L2 bank width (DRAM width, change with care)
+l2_bank_width ?= 512
+
+# L2 interleaving factor (in order of bank_width)
+l2_interleave ?= 16
+
+
+##################
+##  Peripherals ##
+##################
+# Hardware stack size (in Byte)
+stack_hw_size ?= 1024
+
+# Stack size (total, including share and private, 32'h800)
+stack_tot_size ?= 2048

config/config.mk

@@ -131,6 +131,9 @@ spatz_max_trans ?= 32
 # Snitch/FPU max outstanding transactions
 snitch_max_trans ?= 16
 
+# Number of Snitch scalar harts sharing one Spatz per Core Complex (1 or 2)
+num_scalar_per_core ?= 1
+
 
 #########################
 ##  AXI configuration  ##

hardware/cachepool_peripheral/Makefile

@@ -5,7 +5,9 @@
 # Noah Huetter <huettern@iis.ee.ethz.ch>
 
 ROOTDIR=../..
-REGTOOL=`$(ROOTDIR)/install/bender/bender path register_interface`/vendor/lowrisc_opentitan/util/regtool.py
+BENDER ?= bender
+
+REGTOOL=`$(BENDER) path register_interface`/vendor/lowrisc_opentitan/util/regtool.py
 PYTHON3=$(shell which python)
 CLANG_FORMAT=$(shell which clang-format-10.0.1)
 

hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson

@@ -31,6 +31,19 @@
             desc: "Hardware barrier register."
         }]
     },
+    {
+        name: "SPATZ_LOCK",
+        desc: '''Spatz ownership lock for dual-Snitch core complexes. Write 1 to acquire
+        (blocks until granted), write 0 to release.'''
+        swaccess: "ro",
+        hwaccess: "hrw",
+        hwext: "true",
+        fields: [{
+            bits: "31:0",
+            name: "SPATZ_LOCK",
+            desc: "Spatz ownership lock register."
+        }]
+    },
     {
         name: "ICACHE_PREFETCH_ENABLE",
         desc: '''Controls prefetching of the instruction cache.'''