Multi-Scalar Configuration

[DiyouS]

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Summary

This PR adds a new "dual-CC" Core Complex flavor to CachePool: two Snitch scalar harts sharing one Spatz vector/FPU unit, for RLC-style kernels where not every hart needs the vector core
at the same time. cachepool_cc.sv (single-Snitch CC) is untouched — this is a sibling module (cachepool_cc_dual.sv) selected by a new build-time knob.

Two sharing modes are provided:

1. Idle (default at boot): an acc_mux round-robin requests from both Snitches onto Spatz, one request outstanding at a time.
2. Locked: a Snitch acquires exclusive ownership by writing to a dedicated peripheral register (cachepool_spatz_lock); once locked, only the owner's requests are forwarded to Spatz,
   non-owner requests are rejected. A release drains all outstanding Spatz traffic — including vle/vse ops, which don't produce a normal acc_rsp_t completion and need their own tracking —
   before handing ownership back to idle/round-robin.

TODO:

• Add and test more configurations

• Adapt current kernels for dual-scalar core

• Add dual-scalar core configuration into CI

  Hardware

  • New modules: hardware/src/cachepool_cc_dual.sv (dual-Snitch CC, 2× snitch + 1× spatz), hardware/src/cachepool_spatz_lock.sv (ownership arbiter + drain counter + memory-path pass-through
    register cuts), hardware/src/acc_mux.sv (idle round-robin / locked pass-through acc-interface mux).
  • hardware/src/cachepool_tile.sv: restructured gen_core → gen_cc, generate-selecting cachepool_cc vs cachepool_cc_dual per hart count; icache fetch ports, TCDM port counts/AMO handling,
    and hart-id assignment all updated for the variable per-CC hart count.
  • hardware/src/cachepool_cluster.sv, cachepool_group.sv, cachepool_group_noc_wrapper.sv, cachepool_pkg.sv: propagate the new per-CC hart count; renamed NumCore → NumCC for clarity now
    that "core" and "hart" diverge.
  • hardware/cachepool_peripheral/*: new register offset for the Spatz lock acquire/release address (regenerated _reg_pkg.sv/_reg_top.sv/cachepool_peripheral.h).
  • hardware/tb/cachepool_cluster_wrapper.sv, cachepool_monitor.sv: testbench wiring/monitoring updates for the new hart topology.

  Config/build

  • config/cachepool_dual_4g.mk: new config flavor, 4 groups / 64 CCs / 128 harts, num_scalar_per_core=2.
  • config/config.mk: new num_scalar_per_core knob (default 1, unchanged behavior).
  • util/scripts/gen_spatz_cfg.py: cluster.cores now sized by hart count (num_cores * num_scalar_per_core), not CC count, since generate_bootdata.py derives SNRT_BOOT_CORE_COUNT from its
    length.
  • sim/scripts/vsim_core_dual.tcl: new waveform script for the dual-CC signal layout.
  • Makefile: added hw (generate+bootrom+vsim) and all (hw+sw) shortcuts; split clean into clean.data/clean.generate/clean.hw/clean.sw for finer-grained cleaning; make help/README updated
    to match.
  • iis-env.sh/requirements.txt: pin venv to python3.12 (floogen needs >=3.10) and install floogen + pyyaml, needed for the FlooNoC regeneration this config change touches.
  • Bender.yml: register the three new source files.

  Software runtime

  • software/snRuntime/include/spatz_lock.h + src/spatz_lock.c: spatz_lock_acquire()/spatz_lock_release(), raw register ops against the new peripheral offset.
  • snrt_cluster_is_primary() (team.c): identifies host-0 vs host-1 of a CC pair (core_idx % 2 == 0 under SNRT_NUM_SCALAR_PER_CORE == 2, always true otherwise).
  • snrt_cluster_host0_barrier() / snrt_cluster_host1_barrier() (barrier.c): partial-barrier helpers that synchronize only one role across a tile, built on the existing partial-barrier mask
    mechanism.
  • software/CMakeLists.txt / snRuntime/CMakeLists.txt: propagate SNRT_NUM_SCALAR_PER_CORE to both the runtime and sibling test directories (CMake directory-property scoping fix).

  Tests

  • software/tests/spatz-lock-handoff/main.c (new): a lost-update race test that actually proves the lock serializes host0/host1 — both hosts race to add a fixed constant directly into the
    shared Spatz register v0 under lock protection; a lost update (lock failing to exclude concurrent access) yields a detectably wrong final sum, unlike a per-hart-disjoint-slice test which
    can't distinguish real serialization from independently-correct access.
  • software/tests/idotp-32b/main.c: diagnostic tweaks to exercise the lock under an existing kernel (host0 holds the lock for the whole run via snrt_cluster_host0_barrier); l1d_xbar_config
    and one snrt_cluster_hw_barrier call are currently commented out — flagging in case these should be restored/cleaned up before merge.

  Verification

  Confirmed passing in simulation with cachepool_dual_4g: spatz-lock-handoff reports [PASS] pairs=64 len=64, clean [EOC] exit (retval = 0), no assertion failures.

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