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c1ba586
Complete synthetic logical and control instruction milestones
ilehtoranta Oct 4, 2026
86ce18b
Trim trailing blank lines in synthetic suite sources
ilehtoranta Oct 4, 2026
5ef8726
Add cross-model reference audits and correct 68040 T0 tracing
ilehtoranta Oct 4, 2026
c4b924f
Correct 68040 single-word MMU decoding and privilege checks
ilehtoranta Oct 4, 2026
3a673bf
Halt 68000 address-error double faults until reset
ilehtoranta Oct 4, 2026
d69453e
Dispatch 68000 compiled alignment faults before operand effects
ilehtoranta Oct 4, 2026
c6b26b8
Correct 68010 format-8 frame structure and RTE validation
ilehtoranta Oct 4, 2026
ff05918
Resume 68010 word MOVE cycles from format-8 frames
ilehtoranta Oct 4, 2026
2d30bd3
Audit pinned 68000 corpus and correct LINK A7 sampling
ilehtoranta Oct 4, 2026
2fe39d8
Add pinned cross-model WinUAE discovery audit
ilehtoranta Oct 4, 2026
9f03827
Verify WinUAE exception frames and defined status flags
ilehtoranta Oct 4, 2026
fb86a4e
Qualify illegal logical operands across CPU models
ilehtoranta Oct 4, 2026
fa09c0c
Qualify illegal arithmetic and CAS operands
ilehtoranta Oct 4, 2026
424ad4e
Qualify illegal status and MOVES operands
ilehtoranta Oct 4, 2026
66d276e
Qualify invalid integer operands and 68060 debug instructions
ilehtoranta Oct 4, 2026
4a32a1f
Correct PACK and UNPK stack word strides
ilehtoranta Oct 4, 2026
8ffc8df
Qualify 68040 and 68060 trap trace priority
ilehtoranta Oct 4, 2026
e4f8bb6
Qualify 68040 and 68060 translation control masks
ilehtoranta Oct 4, 2026
964266e
Qualify 68040 and 68060 transparent control registers
ilehtoranta Oct 5, 2026
ccac246
Preserve 68060 lock shadows and validate MOVEC control fields
ilehtoranta Oct 5, 2026
f249fe9
Qualify TRAPcc and CHK2 saved PCs in the reference generator
ilehtoranta Oct 5, 2026
eaddcac
Qualify breakpoint exception PCs and share strict reference audits
ilehtoranta Oct 5, 2026
0041aec
Decode unassigned CHK effective addresses as illegal instructions
ilehtoranta Oct 5, 2026
31a6221
Decode illegal line-four instruction encodings before operand effects
ilehtoranta Oct 5, 2026
281b91b
Qualify illegal quick binary and memory shift encodings
ilehtoranta Oct 5, 2026
903f45c
Qualify line-F state transfers and indexed restoration
ilehtoranta Oct 5, 2026
2787ebf
Handle unassigned 68060 F-line categories architecturally
ilehtoranta Oct 5, 2026
e814040
Qualify legal long arithmetic reference encodings and exceptions
ilehtoranta Oct 5, 2026
7845c5e
Qualify word division flags across all CPU models
ilehtoranta Oct 5, 2026
22f31d0
Expose unqualified 68040 access-frame restoration
ilehtoranta Oct 5, 2026
76b63de
Restore 68040 access frames and saved-address MOVEM continuations
ilehtoranta Oct 5, 2026
9fa9f84
Preserve 68040 pending FPU vectors across access-frame returns
ilehtoranta Oct 5, 2026
1290002
Qualify chained 68040 throwaway frames across stack banks
ilehtoranta Oct 5, 2026
a194c12
Fix and qualify 68040 odd-PC returns and address-error frames
ilehtoranta Oct 5, 2026
cb9679d
Qualify 68060 LPSTOP encodings and exception priority
ilehtoranta Oct 5, 2026
dd807db
Qualify LPSTOP reference frames and consolidate duplicate coverage
ilehtoranta Oct 5, 2026
73f94aa
Qualify legal MOVES inputs across selected CPU profiles
ilehtoranta Oct 5, 2026
76c7a65
Qualify legal CAS inputs and 68060 exception PCs
ilehtoranta Oct 5, 2026
d713205
Qualify CAS2 compare aliases and unimplemented frames
ilehtoranta Oct 5, 2026
230009a
Qualify cache instruction encodings and consolidate duplicates
ilehtoranta Oct 5, 2026
7c14dbe
Correct 68040 RTE validation access-fault frames
ilehtoranta Oct 5, 2026
be81a65
Halt 68040 access-fault entry on a second bus fault
ilehtoranta Oct 5, 2026
c469998
Handle 68040 physical faults during batch execution
ilehtoranta Oct 5, 2026
9ab8d56
Qualify 68040 batch-fault coverage and mutation gates
ilehtoranta Oct 5, 2026
36a8edf
Qualify executed 68040 RTE frame repair and retry
ilehtoranta Oct 5, 2026
d99f7c8
Fix 68040 instruction-fetch access frames and qualify restart
ilehtoranta Oct 5, 2026
92922a7
Keep 040 speculative host reads inside their supported boundary
ilehtoranta Oct 5, 2026
dc27536
Prefetch and retain 68040 access-error handler entry
ilehtoranta Oct 5, 2026
32761cc
Qualify 68040 user-stack RTE faults and software repair
ilehtoranta Oct 5, 2026
b884aee
Qualify preserved trace after 68040 RTE repair
ilehtoranta Oct 5, 2026
b59300c
Qualify pending 68040 delivery with preserved trace
ilehtoranta Oct 5, 2026
e26a8cc
Qualify restored user master bit after 68040 RTE repair
ilehtoranta Oct 5, 2026
635ecde
Qualify preserved trace across 68040 CP vectors
ilehtoranta Oct 5, 2026
e522432
Qualify executed 68040 software trace service
ilehtoranta Oct 6, 2026
47d6400
Qualify preserved trace across 68040 user-tail RTE repair
ilehtoranta Oct 6, 2026
5325133
Qualify software trace service after 68040 user-tail repair
ilehtoranta Oct 6, 2026
5e90768
Qualify mixed trace epochs in 68040 throwaway chains
ilehtoranta Oct 6, 2026
78d6dce
Qualify mixed-epoch 68040 RTE validation faults
ilehtoranta Oct 6, 2026
72102e9
Add mixed-epoch 68040 RTE retry discovery
ilehtoranta Oct 6, 2026
2f66bca
Qualify chained 68040 RTE odd-PC SR handoff
ilehtoranta Oct 6, 2026
826351f
Qualify chained 68040 access-frame SR handoff
ilehtoranta Oct 6, 2026
b88f950
Record 68040 CM lifetime software-reference discovery
ilehtoranta Oct 6, 2026
11124e9
Execute scoped 68040 MMU exception entry in CM audit
ilehtoranta Oct 6, 2026
a71460d
Qualify 68060 PCR fields and consolidate proven regression
ilehtoranta Oct 6, 2026
e2c456b
Record 68060 STOP software-reference discovery
ilehtoranta Oct 6, 2026
90e3afa
Qualify 68010 MOVEC and consolidate proven regressions
ilehtoranta Oct 6, 2026
d1d4676
Record 68010 rejected RTE format reference discovery
ilehtoranta Oct 6, 2026
f028c34
Fix 68010 long MOVE fault continuation and qualify restart coverage
ilehtoranta Oct 6, 2026
ea7b5ac
Make 68010 continuation mutation qualification reproducible
ilehtoranta Oct 6, 2026
c3c9fd2
Qualify full-width EXG and consolidate proven regression
ilehtoranta Oct 6, 2026
6ad4db6
Qualify supplied 68040 writeback handler execution
ilehtoranta Oct 6, 2026
e487d2d
Fix and qualify 040 MOVE write-fault recovery
ilehtoranta Oct 6, 2026
0bea1be
Fix and qualify 68030 PMMU privilege priority
ilehtoranta Oct 6, 2026
7160527
Isolate WinUAE audit builds and restore qualification evidence
ilehtoranta Oct 6, 2026
d5d0b3f
Restore broad CPU reference evidence and add isolated audit command
ilehtoranta Oct 6, 2026
cab99ec
Qualify canonical MOVE16 reference inputs and coverage
ilehtoranta Oct 6, 2026
261fbab
Complete supervisor A7 MOVE16 reference qualification
ilehtoranta Oct 6, 2026
e106e6a
Expose 68040 operand read fault frame qualification gap
ilehtoranta Oct 6, 2026
ae7ee8e
Fix 68040 physical operand-read access frames
ilehtoranta Oct 6, 2026
bee4816
Qualify 68040 MOVEM operand-read recovery
ilehtoranta Oct 6, 2026
4863f44
Qualify MOVEM indirect-pointer fault restart
ilehtoranta Oct 6, 2026
79b8841
Prove and consolidate duplicate EXTB regression
ilehtoranta Oct 6, 2026
72800d7
Expose actual 68040 MOVEM write-fault frame gap
ilehtoranta Oct 6, 2026
902b99c
Fix 68040 MOVEM write-fault frames and qualify recovery
ilehtoranta Oct 6, 2026
162d5ce
Expose 020 and 030 address-error frame restoration gap
ilehtoranta Oct 6, 2026
4837ce9
Fix 020 and 030 instruction-prefetch recovery
ilehtoranta Oct 7, 2026
8c471e2
Fix 020/030 RTE validation faults and EC020 map wrapping
ilehtoranta Oct 7, 2026
020629b
Record typed trace-vector recovery qualification
ilehtoranta Oct 7, 2026
4f9024f
Record A7 and saved instruction-pipe qualification
ilehtoranta Oct 7, 2026
eeb0c4d
Record PC-relative operand function-code qualification
ilehtoranta Oct 7, 2026
9137d09
Record indexed MOVE read-stage qualification
ilehtoranta Oct 7, 2026
e81ddd5
Record chained indexed read-fault qualification
ilehtoranta Oct 7, 2026
6a5e478
Record full-indexed read-structure qualification
ilehtoranta Oct 7, 2026
e7e10b2
Record indexed register and alias qualification
ilehtoranta Oct 7, 2026
16f0940
Record signed indexed read-boundary qualification
ilehtoranta Oct 7, 2026
9cd8a64
Record all-structure chained indexed fault qualification
ilehtoranta Oct 7, 2026
d59822f
Record three-word private pipe qualification
ilehtoranta Oct 7, 2026
795dc75
Record nested operand and trace-vector provenance
ilehtoranta Oct 7, 2026
dd072e7
Record high and wrapped private operand-frame transport
ilehtoranta Oct 7, 2026
1e1ab44
Record private frame entry and state-load HALT qualification
ilehtoranta Oct 7, 2026
72d23ed
Prove and consolidate CMPM alias and stack regressions
ilehtoranta Oct 7, 2026
b03f1b4
Normalize CMPM verifier and record final audit identity
ilehtoranta Oct 7, 2026
1791579
Record full indexed and chained private pipe qualification
ilehtoranta Oct 7, 2026
032a466
Record private fault frame relocation defect and isolated correction
ilehtoranta Oct 7, 2026
d64a873
Qualify private recovery A7 aliases and returned CCR
ilehtoranta Oct 7, 2026
196c7de
Qualify full indexed and chained nested trace provenance
ilehtoranta Oct 7, 2026
44637f3
Record private returned privilege and stack-mode qualification
ilehtoranta Oct 7, 2026
7fe695f
Qualify private refault cycle provenance and scope restoration
ilehtoranta Oct 7, 2026
34b4e8b
Record private returned trace policy and unresolved reference outcomes
ilehtoranta Oct 7, 2026
6b64320
Record complete combined private recovery qualification
ilehtoranta Oct 7, 2026
2366754
Execute canonical 030 fault recovery trace reference
ilehtoranta Oct 7, 2026
1d4339e
Audit compatible 030 trace recovery and reference disagreement
ilehtoranta Oct 7, 2026
5268a4f
Prove and consolidate 68010 EXTB availability coverage
ilehtoranta Oct 7, 2026
6bb7ef8
Record indexed returned-bank control and pending complete gate
ilehtoranta Oct 7, 2026
b4a60c6
Complete indexed return-bank audit and consolidate address arithmetic
ilehtoranta Oct 7, 2026
35e2693
Record latest corrected combined recovery replay and provisional audit
ilehtoranta Oct 7, 2026
125f5a7
Make address arithmetic consolidation independently reproducible
ilehtoranta Oct 7, 2026
1fcc8c0
Start current CPU-suite qualification on latest private recovery source
ilehtoranta Oct 7, 2026
77d5f00
Qualify complete recovery replay on latest private CPU
ilehtoranta Oct 7, 2026
3439d71
Qualify current full CPU suite on latest private recovery source
ilehtoranta Oct 7, 2026
8e020e9
Discriminate returned A7 postincrement bank policies
ilehtoranta Oct 7, 2026
d510c54
Investigate native 030 A7 fault-recovery fixup behavior
ilehtoranta Oct 7, 2026
b0a930c
Isolate native A7 fault-recovery fixup ordering cause
ilehtoranta Oct 7, 2026
714ee99
Maintain reproducible native 030 A7 recovery discovery audit
ilehtoranta Oct 7, 2026
8948313
Refresh native A7 audit evidence after fixture whitespace cleanup
ilehtoranta Oct 7, 2026
073d1f4
Remove fixture blank-line whitespace and pin fresh A7 audit evidence
ilehtoranta Oct 7, 2026
8b6418f
Prove shared SUBA indirect sign-extension replacement coverage
ilehtoranta Oct 7, 2026
4ee523d
Retire proven redundant SUBA indirect word and long regressions
ilehtoranta Oct 7, 2026
2d47495
Consolidate CMPA displacement regression with shared audit infrastruc…
ilehtoranta Oct 7, 2026
b403a8c
Observe native 030 source-fault recovery before MOVE memory destinations
ilehtoranta Oct 7, 2026
b8e85ae
Qualify private MOVE memory-destination read recovery
ilehtoranta Oct 7, 2026
23f9e8d
Qualify native MOVE transfer faults and expose private write mapping gap
ilehtoranta Oct 7, 2026
57b9e91
Qualify private pending MOVE write recovery without source replay
ilehtoranta Oct 7, 2026
e0cdd4e
Qualify private pending-write software edits and refault protocols
ilehtoranta Oct 7, 2026
361ea5a
Audit native pending-write handlers and isolate refault PC disagreement
ilehtoranta Oct 7, 2026
8aa9083
Qualify private all-width source recovery and chained MOVE writes
ilehtoranta Oct 7, 2026
e8168c4
Qualify private pending-write saved pipes and retained word edits
ilehtoranta Oct 7, 2026
1ac67e2
Record full production baseline and exact private discovery gate
ilehtoranta Oct 8, 2026
2b55c6d
Require consolidation reports and record complete private validation
ilehtoranta Oct 8, 2026
bbce629
Qualify cold pending-write frame restoration and rejection
ilehtoranta Oct 8, 2026
ab1d1cc
Qualify pending-write frame validation and load faults
ilehtoranta Oct 8, 2026
cae17a9
Account for broad reference first failures without promoting coverage
ilehtoranta Oct 8, 2026
133f639
Compose broad reference corrections and expose later failures
ilehtoranta Oct 8, 2026
d7f330c
Qualify coprocessor ID priority in broad native references
ilehtoranta Oct 8, 2026
375c6d8
Fix reserved MOVE16 exceptions and consolidate AND coverage
ilehtoranta Oct 8, 2026
4aa9db3
Qualify 040 MOVEM register-mask fault recovery
ilehtoranta Oct 8, 2026
37dbb3a
Reproduce 040 MOVES physical fault frame gaps
ilehtoranta Oct 8, 2026
d960ff2
Correct 040 MOVES read fault transfer attributes
ilehtoranta Oct 8, 2026
6cddeab
Correct 040 MOVES normal-space write fault recovery
ilehtoranta Oct 8, 2026
61fd6ae
Promote 040 nested integer writeback fault coverage
ilehtoranta Oct 8, 2026
3dd2640
Correct 040 MOVE16 physical line-write recovery
ilehtoranta Oct 8, 2026
0a55fa1
Consolidate NOT displacement semantic regressions
ilehtoranta Oct 8, 2026
b7ccd69
Qualify private pending-write validation continuations
ilehtoranta Oct 8, 2026
af64562
Qualify private validation exception-entry faults
ilehtoranta Oct 8, 2026
b74bf3b
Qualify changed input to private write validation
ilehtoranta Oct 8, 2026
965aa7c
Qualify private returned-bank pending-write refaults
ilehtoranta Oct 8, 2026
9430fc4
Qualify actual MOVE secondary entry faults
ilehtoranta Oct 8, 2026
c284b94
Consolidate EOR byte postincrement semantic regression
ilehtoranta Oct 8, 2026
66968c2
Record milestone six completion requirements and open gates
ilehtoranta Oct 8, 2026
807756a
Link current seeded and independent reference evidence
ilehtoranta Oct 8, 2026
51444ea
Reject duplicate synthetic audit model selections
ilehtoranta Oct 8, 2026
434ec10
Refresh six required MOVE mutation witnesses
ilehtoranta Oct 8, 2026
ea18c2c
Link full qualification and later failed-reference observations
ilehtoranta Oct 8, 2026
3a5314f
Consolidate captured ANDI displacement regression
ilehtoranta Oct 8, 2026
56c0a69
Record per-case failed-reference witnesses
ilehtoranta Oct 8, 2026
55fe8b7
Consolidate aliased MOVEA word displacement regression
ilehtoranta Oct 8, 2026
86469f7
Bind retirement evidence to executed assemblies and methods
ilehtoranta Oct 8, 2026
90f0cb2
Record current-build seeded and software-reference qualification
ilehtoranta Oct 8, 2026
4b3923d
Qualify deep-audit rejection guards against current assemblies
ilehtoranta Oct 8, 2026
29922b7
Qualify complete current CPU and reference evidence
ilehtoranta Oct 8, 2026
ac4c18f
Qualify private C021 return metadata guards
ilehtoranta Oct 8, 2026
31b3363
Maintain strict private RTE metadata qualification and replay
ilehtoranta Oct 8, 2026
45e732a
Record combined private candidate qualification and full replay start
ilehtoranta Oct 8, 2026
4ca734b
Qualify combined candidate consumers and same-build references
ilehtoranta Oct 8, 2026
df2a9ec
Record combined candidate API comparison
ilehtoranta Oct 8, 2026
f638541
Qualify private predecrement MOVE write recovery
ilehtoranta Oct 8, 2026
de25240
Qualify newer private candidate consumers and references
ilehtoranta Oct 8, 2026
b92f6f5
Record complete predecessor CPU qualification
ilehtoranta Oct 8, 2026
ebad4de
Update 040 fault inventory coverage descriptions
ilehtoranta Oct 8, 2026
b50aee2
Qualify private predecrement MOVE read recovery
ilehtoranta Oct 8, 2026
ec3c285
Qualify private read candidate references and consumers
ilehtoranta Oct 8, 2026
df9de9b
Make private predecrement recovery audit reproducible
ilehtoranta Oct 8, 2026
5ce0f50
Identify pinned private audit reproduction checkout
ilehtoranta Oct 8, 2026
de4bcc2
Qualify mixed-width nested 040 writeback recovery
ilehtoranta Oct 8, 2026
bfceb08
Record complete private write-candidate qualification
ilehtoranta Oct 8, 2026
2c3b1d2
Qualify supplied 040 user returns and same-width CCRs
ilehtoranta Oct 8, 2026
b8578b6
Qualify remaining supplied 040 user-frame widths
ilehtoranta Oct 8, 2026
a2d4b3b
Qualify differing nested writeback function codes
ilehtoranta Oct 8, 2026
8826c5e
Record complete private read-candidate qualification
ilehtoranta Oct 8, 2026
33e712f
Qualify supplied user-M nested writeback returns
ilehtoranta Oct 8, 2026
dd01067
Qualify differing FCs for supplied user-M returns
ilehtoranta Oct 8, 2026
0f9138f
Qualify repeated nested writeback fault unwinds
ilehtoranta Oct 8, 2026
02e6c58
Maintain strict nested writeback audit and replay
ilehtoranta Oct 8, 2026
5a6eda3
Prove repeated nested faults detect wrong saved PC
ilehtoranta Oct 8, 2026
a96d16a
Record complete nested writeback qualification
ilehtoranta Oct 8, 2026
d993b9c
Qualify differing function codes through repeated faults
ilehtoranta Oct 8, 2026
65dfea8
Qualify completed first-read fault recovery
ilehtoranta Oct 8, 2026
09b3736
Qualify executed persistent read mapping repair
ilehtoranta Oct 9, 2026
bb3a085
Maintain strict first-read recovery qualification
ilehtoranta Oct 9, 2026
567246d
Expose lost and unrelated CP vectors after task transfer
ilehtoranta Oct 9, 2026
b6ed3ff
Qualify private suspended-delivery context snapshot candidate
ilehtoranta Oct 9, 2026
760c836
Record context candidate reference and standard consumer qualification
ilehtoranta Oct 9, 2026
0e10bb9
Qualify full private context candidate against retained coverage
ilehtoranta Oct 9, 2026
d1dbf94
Qualify suspended context delivery across all CCR images
ilehtoranta Oct 9, 2026
39ddb61
Link all-CCR candidate to same-build reference audits
ilehtoranta Oct 9, 2026
225d826
Record full all-CCR reference qualification
ilehtoranta Oct 9, 2026
b1fcdec
Clarify remaining context qualification without weakening its gate
ilehtoranta Oct 9, 2026
ea54036
Qualify recovered native Workbench consumer replays
ilehtoranta Oct 9, 2026
69497de
Preserve independent pending deliveries in copied CPU contexts
ilehtoranta Oct 9, 2026
9a09783
Align remaining qualification descriptions with approved context fix
ilehtoranta Oct 9, 2026
e15a332
Accept qualified coverage and explicitly defer unresolved behavior
ilehtoranta Oct 9, 2026
2822e80
Merge pull request #22 from ilehtoranta/codex/synthetic-reference-qua…
ilehtoranta Oct 9, 2026
a773286
Merge mainline CPU support into synthetic qualification suite
ilehtoranta Oct 9, 2026
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6 changes: 6 additions & 0 deletions .gitattributes
Original file line number Diff line number Diff line change
@@ -0,0 +1,6 @@
# Unified patch context needs its single-space blank lines; keep evidence bytes stable.
scripts/reference/m68020-predecrement-write-candidate.patch text eol=lf whitespace=-blank-at-eol
scripts/reference/m68020-predecrement-read-candidate.patch text eol=lf whitespace=-blank-at-eol
scripts/reference/m68020-read-write-recovery-candidate.patch text eol=lf whitespace=-blank-at-eol,-blank-at-eof
scripts/reference/m68020-private-predecrement-manifest.json text eol=lf
scripts/reference/m68040-context-pending-candidate.patch text eol=lf whitespace=-blank-at-eol
4 changes: 2 additions & 2 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -58,14 +58,14 @@ jobs:

- name: Pack Copper68k NuGet
shell: pwsh
run: .\scripts\nuget\pack-copper68k.ps1
run: .\scripts\nuget\pack-copper68k.ps1 -SkipTests

- name: Test Copper68k
env:
COPPER68K_SYNTHETIC_REPORT_DIR: ${{ github.workspace }}/artifacts/synthetic-suite
run: dotnet test Copper68k.Tests\Copper68k.Tests.csproj --configuration Release

- name: Require complete synthetic milestone coverage
- name: Require accepted synthetic coverage and report deferred qualification
shell: pwsh
run: ./scripts/test-copper68k-synthetic.ps1 -ValidateReportsOnly -OutputDirectory artifacts/synthetic-suite

Expand Down
333 changes: 333 additions & 0 deletions Copper68k.Tests/M68000JitDirectZeroWaitTests.cs

Large diffs are not rendered by default.

65 changes: 3 additions & 62 deletions Copper68k.Tests/M68010InterpreterTests.cs
Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,8 @@ public void Format8RteConsumesEntireFrameAndRetainsLiveStackBank()
bus.WriteLong(12, 0x2000);
var cpu = new M68010Interpreter(bus); cpu.Reset(CodeBase, 0x3000); cpu.State.A[1] = 1;
cpu.ExecuteInstruction();
// An error handler may explicitly change the stacked continuation PC.
// Exercise an unmarked structural frame, not a marked MOVE restart.
bus.WriteWord(cpu.State.A[7] + 28, 0);
bus.WriteLong(cpu.State.A[7] + 2, CodeBase + 2);
cpu.ExecuteInstruction();
Assert.Equal(0x3000u, cpu.State.A[7]);
Expand Down Expand Up @@ -65,66 +66,6 @@ public void FactoryCreatesM68010CoreWithoutM68020StackMode()
Assert.False(interpreter.State.M68020StackModeEnabled);
}

[Fact]
public void MovecTransfersVectorBaseRegister()
{
var bus = new ZeroWaitCodeBus();
WriteWords(
bus,
CodeBase,
0x4E7B, 0x0801, // MOVEC D0,VBR
0x4E7A, 0x1801); // MOVEC VBR,D1
var cpu = new M68010Interpreter(bus);
cpu.Reset(CodeBase, 0x3000);
cpu.State.D[0] = 0x0000_0400;
cpu.ExecuteInstruction();
cpu.ExecuteInstruction();
Assert.Equal(0x0000_0400u, cpu.State.VectorBaseRegister);
Assert.Equal(0x0000_0400u, cpu.State.D[1]);
Assert.False(cpu.State.M68020StackModeEnabled);
}

[Theory]
[InlineData((ushort)0x000, 0xFFFF_FFFEu, 0x0000_0006u)]
[InlineData((ushort)0x001, 0xFFFF_FFFDu, 0x0000_0005u)]
[InlineData((ushort)0x801, 0x1234_5678u, 0x1234_5678u)]
public void MovecTransfersSupportedControlRegisters(
ushort controlRegister,
uint sourceValue,
uint expectedValue)
{
var bus = new ZeroWaitCodeBus();
WriteWords(
bus,
CodeBase,
0x4E7B, controlRegister, // MOVEC D0,control
0x4E7A, (ushort)(0x1000 | controlRegister)); // MOVEC control,D1
var cpu = new M68010Interpreter(bus);
cpu.Reset(CodeBase, 0x3000);
cpu.State.D[0] = sourceValue;

cpu.ExecuteInstruction();
cpu.ExecuteInstruction();

Assert.Equal(expectedValue, cpu.State.D[1]);
Assert.Equal(CodeBase + 8u, cpu.State.ProgramCounter);
}

[Fact]
public void MovecVectorBaseToA7UpdatesActiveSupervisorStackPointer()
{
var bus = new ZeroWaitCodeBus();
WriteWords(bus, CodeBase, 0x4E7A, 0xF801); // MOVEC VBR,A7
var cpu = new M68010Interpreter(bus);
cpu.Reset(CodeBase, 0x3000);
cpu.State.VectorBaseRegister = 0x0000_4800;

cpu.ExecuteInstruction();

Assert.Equal(0x0000_4800u, cpu.State.A[7]);
Assert.Equal(0x0000_4800u, cpu.State.SupervisorStackPointer);
}

[Fact]
public void MovecInUserModeRaisesPrivilegeViolationWithoutChangingControlRegister()
{
Expand Down Expand Up @@ -268,7 +209,7 @@ public void OddWordReadRaisesFormat8AddressErrorFrame()
Assert.Equal(0x800Cu, bus.ReadWord(0x2FCC));
Assert.Equal(0x1105, bus.ReadWord(0x2FCE));
Assert.Equal(1u, bus.ReadLong(0x2FD0));
Assert.Equal(0x3211, bus.ReadWord(0x2FDE));
Assert.Equal(0, bus.ReadWord(0x2FDE)); // Instruction input is unqualified.
}

[Fact]
Expand Down
39 changes: 0 additions & 39 deletions Copper68k.Tests/M68020AddressSourceTests.cs
Original file line number Diff line number Diff line change
Expand Up @@ -46,18 +46,6 @@ public void AddToIndirectMemoryWritesSelectedWidthAndPreservesSource(ushort opco
Assert.Equal(source, cpu.State.D[0]); Assert.Equal(flags, cpu.State.StatusRegister & 31); Assert.Equal(CodeBase + 2, cpu.State.ProgramCounter);
}

[Theory]
[InlineData(0xFFFFu, 0xFFFF, 0x11)] [InlineData(0xFFFFFFFFu, 0xFFFF, 0x14)]
[InlineData(0u, 1, 0x19)]
public void CmpaWordDisplacementComparesSignExtendedSourceAgainstFullAddress(uint destination, ushort source, int flags)
{
var bus = new ZeroWaitCodeBus(); WriteWords(bus, CodeBase, 0xB2E8, 0xFFFE); WriteWords(bus, 0x2000, source);
using var cpu = M68kCoreFactory.Default.CreateA1200Ec020(bus);
cpu.Reset(CodeBase, 0x3000); cpu.State.A[0] = 0x2002; cpu.State.A[1] = destination; cpu.State.StatusRegister = 0x201F;
cpu.ExecuteInstruction(); Assert.Equal(flags, cpu.State.StatusRegister & 31);
Assert.Equal(destination, cpu.State.A[1]); Assert.Equal(CodeBase + 4, cpu.State.ProgramCounter);
}

[Theory]
[InlineData(0x5270, 0xFFFF, 0, 0x15)] [InlineData(0x5370, 0, 0xFFFF, 0x19)]
[InlineData(0x5070, 0x7FF8, 0x8000, 10)]
Expand Down Expand Up @@ -102,18 +90,6 @@ public void ImmediateIndexedBitOperationsReadTheOriginalBitAndKeepOtherFlags(ush
Assert.Equal(CodeBase + 6, cpu.State.ProgramCounter);
}

[Theory]
[InlineData(0x90D3, 0xFFFE, 0, 0x1002u)]
[InlineData(0x91D3, 0, 2, 0xFFEu)]
public void SubaIndirectSignExtendsWordsAndLeavesCcrUntouched(ushort opcode, ushort hi, ushort lo, uint expected)
{
var bus = new ZeroWaitCodeBus(); WriteWords(bus, CodeBase, opcode); WriteWords(bus, 0x2000, hi, lo);
using var cpu = M68kCoreFactory.Default.Create(M68kCpuModel.M68EC020, bus);
cpu.Reset(CodeBase, 0x3000); cpu.State.A[3] = 0x2000; cpu.State.A[0] = 0x1000; cpu.State.StatusRegister = 0x201F;
cpu.ExecuteInstruction(); Assert.Equal(expected, cpu.State.A[0]); Assert.Equal(0x2000u, cpu.State.A[3]);
Assert.Equal(0x201F, cpu.State.StatusRegister); Assert.Equal(CodeBase + 2, cpu.State.ProgramCounter);
}

[Theory]
[InlineData(0x2060, 0)] [InlineData(0x2260, 1)]
public void MoveaPredecrementLatchesSourceBeforeDestinationAndKeepsFlags(ushort opcode, int destination)
Expand All @@ -140,21 +116,6 @@ public void CmpiPostIncrementPreservesExtendAndUsesByteStackStride(ushort opcode
Assert.Equal(0x2000u + stride, cpu.State.A[opcode & 7]); Assert.Equal(CodeBase + 4, cpu.State.ProgramCounter);
}

[Theory]
[InlineData(0xC012, 0xFFFF00F0u)]
[InlineData(0xC052, 0xFFFFF0A5u)]
[InlineData(0xC092, 0xF0A55A0Fu)]
public void AndAddressIndirectUsesSelectedWidthAndPreservesExtend(ushort opcode, uint expected)
{
var bus = new ZeroWaitCodeBus(); WriteWords(bus, CodeBase, opcode); WriteWords(bus, 0x2000, 0xF0A5, 0x5A0F);
using var cpu = M68kCoreFactory.Default.Create(M68kCpuModel.M68EC020, bus);
cpu.Reset(CodeBase, 0x3000); cpu.State.A[2] = 0x2000; cpu.State.D[0] = 0xFFFF00FF;
if (opcode != 0xC012) cpu.State.D[0] = uint.MaxValue;
cpu.State.StatusRegister = 0x2017; cpu.ExecuteInstruction();
Assert.Equal(expected, cpu.State.D[0]); Assert.Equal(0x18, cpu.State.StatusRegister & 31);
Assert.Equal(0x2000u, cpu.State.A[2]); Assert.Equal(CodeBase + 2, cpu.State.ProgramCounter);
}

[Theory]
[InlineData(9u, 0x80, 0x1F)]
[InlineData(15u, 0x80, 0x1B)]
Expand Down
10 changes: 7 additions & 3 deletions Copper68k.Tests/M68020BrianOperandTests.cs
Original file line number Diff line number Diff line change
Expand Up @@ -184,15 +184,19 @@ public void OrBriefIndexedResolvesAliasedDataIndexBeforeStore()
}

[Fact]
public void OrFullIndexedRemainsExplicitlyUnsupported()
public void OrFullIndexedExecutesWithLongBaseDisplacementAndPreservesUpperWord()
{
var bus = new ZeroWaitCodeBus();
WriteWords(bus, 0xF80000, 0x8C70, 0x0130, 0, 0x20);
using var cpu = M68kCoreFactory.Default.CreateA1200Ec020(bus);
cpu.Reset(0xF80000, 0x4000);
cpu.State.D[6] = 0x12345678;
Assert.Throws<UnsupportedM68kTimingException>(() => cpu.ExecuteInstruction());
Assert.Equal(0x12345678u, cpu.State.D[6]);
cpu.State.A[0] = 0x5000; cpu.State.D[0] = 0;
bus.WriteWord(0x5020, 0x8001);
cpu.ExecuteInstruction();
Assert.Equal(0x1234D679u, cpu.State.D[6]);
Assert.Equal(0xF80008u, cpu.State.ProgramCounter);
Assert.Equal(8, cpu.State.StatusRegister & 15);
}

[Theory]
Expand Down
29 changes: 0 additions & 29 deletions Copper68k.Tests/M68020CmpmTests.cs
Original file line number Diff line number Diff line change
Expand Up @@ -44,35 +44,6 @@ public void CmpmComparesSelectedWidthPreservesExtendAndDoesNotWriteMemory(int pr
Assert.Equal(5, cpu.State.Cycles);
}

[Theory]
[InlineData(0)] [InlineData(1)] [InlineData(2)]
public void AliasedAddressRegisterUsesTheNextOperandAfterSourceIncrement(int size)
{
var bus = new ZeroWaitCodeBus();
WriteWords(bus, CodeBase, (ushort)(0xB108 | size << 6));
Store(bus, 0x2000, size, 0);
Store(bus, 0x2000 + (1u << size), size, 1);
using var cpu = Create(bus, 1);
cpu.Reset(CodeBase, 0x4000); cpu.State.A[0] = 0x2000; cpu.State.StatusRegister = 0x201F;

cpu.ExecuteInstruction();

Assert.Equal(0x2000u + (2u << size), cpu.State.A[0]);
Assert.Equal(0x10, cpu.State.StatusRegister & 31);
}

[Fact]
public void ByteStackRegisterUsesTwoByteStrideForBothAliasedOperands()
{
var bus = new ZeroWaitCodeBus(); WriteWords(bus, CodeBase, 0xBF0F);
WriteWords(bus, 0x4000, 0x0080, 0x0180);
using var cpu = Create(bus, 1);
cpu.Reset(CodeBase, 0x4000); cpu.State.StatusRegister = 0x201F;
cpu.ExecuteInstruction();
Assert.Equal(0x4004u, cpu.State.A[7]);
Assert.Equal(0x10, cpu.State.StatusRegister & 31);
}

private static IM68kCore Create(ZeroWaitCodeBus bus, int profile) => profile switch
{
0 => M68kCoreFactory.Default.Create(M68kCpuModel.M68020, bus),
Expand Down
112 changes: 0 additions & 112 deletions Copper68k.Tests/M68020HdfBootTests.cs
Original file line number Diff line number Diff line change
Expand Up @@ -170,118 +170,6 @@ public void MoveByteDisplacementToPredecrementReadsAliasedSourceBeforeUpdatingAd
}
}

[Theory]
[InlineData(M68kCpuModel.M68020)]
[InlineData(M68kCpuModel.M68EC020)]
[InlineData(M68kCpuModel.M68030)]
[InlineData(M68kCpuModel.M68040)]
public void MoveaWordDisplacementSignExtendsBeforeOverwritingAliasedBase(M68kCpuModel model)
{
foreach (var value in new ushort[] { 0x8001, 0x7FFF, 0 })
foreach (var displacement in new[] { -8, 8 })
{
var bus = new Copper68kTestBus(0x10000);
bus.WriteWords(0x1000, 0x3269, (ushort)displacement); // MOVEA.W (d16,A1),A1
var address = (uint)(0x3000 + displacement);
bus.WriteWord(address, value);
using var cpu = M68kCoreFactory.Default.Create(model, bus);
cpu.Reset(0x1000, 0x7000);
cpu.State.A[1] = 0x3000;
cpu.State.StatusRegister = 0x271F;
cpu.ExecuteInstruction();
Assert.Equal(value == 0x8001 ? 0xFFFF8001u : (uint)value, cpu.State.A[1]);
Assert.Equal(value, bus.ReadWord(address));
Assert.Equal(0x271F, cpu.State.StatusRegister);
Assert.Equal(0x1004u, cpu.State.ProgramCounter);
}
}

[Theory]
[InlineData(M68kCpuModel.M68020)]
[InlineData(M68kCpuModel.M68EC020)]
[InlineData(M68kCpuModel.M68030)]
[InlineData(M68kCpuModel.M68040)]
public void NotLongDisplacementUpdatesOnlyTheLongAndPreservesExtend(M68kCpuModel model)
{
foreach (var value in new uint[] { 0, 0xFFFFFFFF, 0x92345678 })
foreach (var displacement in new[] { -8, 8 })
{
var bus = new Copper68kTestBus(0x10000);
bus.WriteWords(0x1000, 0x46AD, (ushort)displacement);
var address = (uint)(0x3000 + displacement);
bus.WriteWord(address - 2, 0xAAAA);
bus.WriteLong(address, value);
bus.WriteWord(address + 4, 0xBBBB);
using var cpu = M68kCoreFactory.Default.Create(model, bus);
cpu.Reset(0x1000, 0x7000);
cpu.State.A[5] = 0x3000;
cpu.State.StatusRegister = 0x271F;
cpu.ExecuteInstruction();
Assert.Equal(~value, bus.ReadLong(address));
Assert.Equal(0xAAAA, bus.ReadWord(address - 2));
Assert.Equal(0xBBBB, bus.ReadWord(address + 4));
Assert.Equal(value == 0 ? 0x2718 : value == 0xFFFFFFFF ? 0x2714 : 0x2710, cpu.State.StatusRegister);
Assert.Equal(0x1004u, cpu.State.ProgramCounter);
Assert.Equal(0x3000u, cpu.State.A[5]);
}
}

[Theory]
[InlineData(M68kCpuModel.M68020)]
[InlineData(M68kCpuModel.M68EC020)]
[InlineData(M68kCpuModel.M68030)]
[InlineData(M68kCpuModel.M68040)]
public void AddaWordAddressRegisterSignExtendsAndAllowsAliasing(M68kCpuModel model)
{
foreach (var source in new uint[] { 0x12348000, 0xFFFF7FFF })
foreach (var alias in new[] { false, true })
{
var bus = new Copper68kTestBus(0x10000);
bus.WriteWord(0x1000, (ushort)(alias ? 0xD4CA : 0xD4CD));
using var cpu = M68kCoreFactory.Default.Create(model, bus);
cpu.Reset(0x1000, 0x7000);
cpu.State.A[2] = alias ? source : 0x3000;
cpu.State.A[5] = source;
cpu.State.StatusRegister = 0x271F;
cpu.ExecuteInstruction();
var increment = source == 0x12348000 ? -32768 : 32767;
Assert.Equal(unchecked((uint)((alias ? source : 0x3000) + increment)), cpu.State.A[2]);
Assert.Equal(source, cpu.State.A[5]);
Assert.Equal(0x271F, cpu.State.StatusRegister);
Assert.Equal(0x1002u, cpu.State.ProgramCounter);
}
}

[Theory]
[InlineData(M68kCpuModel.M68020)]
[InlineData(M68kCpuModel.M68EC020)]
[InlineData(M68kCpuModel.M68030)]
[InlineData(M68kCpuModel.M68040)]
public void AndiLongDisplacementConsumesLongImmediateAndPreservesExtend(M68kCpuModel model)
{
foreach (var mask in new uint[] { 0, 0x80123456, 0x7FFFFFFF })
foreach (var displacement in new[] { -8, 8 })
{
var bus = new Copper68kTestBus(0x10000);
bus.WriteWords(0x1000, 0x02A9, (ushort)(mask >> 16), (ushort)mask, (ushort)displacement);
var address = (uint)(0x3000 + displacement);
bus.WriteWord(address - 2, 0xAAAA);
bus.WriteLong(address, 0xFFFFFFFF);
bus.WriteWord(address + 4, 0xBBBB);
using var cpu = M68kCoreFactory.Default.Create(model, bus);
cpu.Reset(0x1000, 0x7000);
cpu.State.A[1] = 0x3000;
cpu.State.StatusRegister = 0x271F;
cpu.ExecuteInstruction();
Assert.Equal(mask, bus.ReadLong(address));
Assert.Equal(0xAAAA, bus.ReadWord(address - 2));
Assert.Equal(0xBBBB, bus.ReadWord(address + 4));
Assert.Equal(mask == 0 ? 0x2714 : mask == 0x80123456 ? 0x2718 : 0x2710, cpu.State.StatusRegister);
Assert.Equal(0x1008u, cpu.State.ProgramCounter);
Assert.Equal(0x3000u, cpu.State.A[1]);
}
}

[Theory]
[InlineData(M68kCpuModel.M68020)]
[InlineData(M68kCpuModel.M68EC020)]
Expand Down
16 changes: 0 additions & 16 deletions Copper68k.Tests/M68020InterpreterTests.cs
Original file line number Diff line number Diff line change
Expand Up @@ -39,22 +39,6 @@ public void MovecTransfersVectorBaseRegister()
Assert.Equal(12, cpu.State.Cycles);
}
[Fact]
public void M68020ExecutesM68020OnlyExtbLong()
{
var bus = new ZeroWaitCodeBus();
WriteWords(bus, CodeBase, 0x49C0); // EXTB.L D0
var cpu = new M68020Interpreter(bus, M68020CpuProfile.OcsAccelerator14Mhz);
cpu.Reset(CodeBase, 0x3000);
cpu.State.D[0] = 0x0000_0080;
cpu.ExecuteInstruction();
Assert.Equal(CodeBase + 2u, cpu.State.ProgramCounter);
Assert.Equal(0xFFFF_FF80u, cpu.State.D[0]);
Assert.True(cpu.State.GetFlag(M68kCpuState.Negative));
Assert.False(cpu.State.GetFlag(M68kCpuState.Zero));
Assert.False(cpu.State.GetFlag(M68kCpuState.Overflow));
Assert.False(cpu.State.GetFlag(M68kCpuState.Carry));
}
[Fact]
public void MovecUnsupportedControlRegisterRaisesIllegalWithoutClobberingDestination()
{
var bus = new ZeroWaitCodeBus();
Expand Down
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