spec(port): multi_led_test as .t27 - #6243
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…/multi_led_test.t27 (Closes #6215) Ports the 24-bit wrapping counter, the per-LED bit selection (led0..led5 and led7 from counter bits, led8 tied low) as pure functions in module trinity_top. Checked with t27c from this tree and Zig 0.16.0: typecheck OK, spec-status IMPLEMENTED, gen-verilog emits one `module trinity_top (`, test-report 6/6, 0 BLOCKED. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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Closes #6215
Adds
specs/port/trinity/fpga/openxc7-synth/multi_led_test.t27, the port offpga/openxc7-synth/multi_led_test.v(gHashTag/trinity at 8afec86b8da9). One file, nothing else.Ported: the 24-bit counter with wrap (
counter_next), the LED-from-bit selection (led_from_bit,led0_level,led7_level), andled8tied low. Module nametrinity_topkept.Checks, from this branch with
t27cbuilt from the same tree and Zig 0.16.0:t27c typecheck: OK (0 errors, 0 warnings)t27c spec-status: IMPLEMENTEDt27c gen-verilog | grep -cE '^module trinity_top ?\(': 1t27c test-report: 6 tests, 6 pass, 0 BLOCKEDNot checked: CI result is pending; the generated Verilog was not synthesized.
🤖 Generated with Claude Code