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spec(port): multi_led_test as .t27 - #6243

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dmitrii-f-t27 merged 1 commit into
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spec/port-multi-led-test-6215
Oct 4, 2026
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dmitrii-f-t27 merged 1 commit into
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spec/port-multi-led-test-6215

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Closes #6215

Adds specs/port/trinity/fpga/openxc7-synth/multi_led_test.t27, the port of fpga/openxc7-synth/multi_led_test.v (gHashTag/trinity at 8afec86b8da9). One file, nothing else.

Ported: the 24-bit counter with wrap (counter_next), the LED-from-bit selection (led_from_bit, led0_level, led7_level), and led8 tied low. Module name trinity_top kept.

Checks, from this branch with t27c built from the same tree and Zig 0.16.0:

  • t27c typecheck: OK (0 errors, 0 warnings)
  • t27c spec-status: IMPLEMENTED
  • t27c gen-verilog | grep -cE '^module trinity_top ?\(': 1
  • t27c test-report: 6 tests, 6 pass, 0 BLOCKED

Not checked: CI result is pending; the generated Verilog was not synthesized.

🤖 Generated with Claude Code

…/multi_led_test.t27 (Closes #6215)

Ports the 24-bit wrapping counter, the per-LED bit selection (led0..led5 and
led7 from counter bits, led8 tied low) as pure functions in module trinity_top.

Checked with t27c from this tree and Zig 0.16.0: typecheck OK, spec-status
IMPLEMENTED, gen-verilog emits one `module trinity_top (`, test-report 6/6, 0 BLOCKED.

Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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PR Dashboard

Generated at: 2026-10-04 19:30:47 UTC

Summary

Status Count
Total Open PRs 45
PRs with Failing Checks 30
PRs with All Checks Green 15
READY 12
FAILING 30
PENDING 0
NO CHECKS YET 0

These columns do not partition: 12 + 30 + 0 + 0 = 42, and there are 45 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=8597b6ded596 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@dmitrii-f-t27
dmitrii-f-t27 merged commit 77e5c44 into master Oct 4, 2026
23 of 25 checks passed
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Port gHashTag/trinity:fpga/openxc7-synth/multi_led_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/multi_led_test.t27

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