Ability to import specific module from Verilog/model from BLIF without making its io the block's IO - #398
Open
mdko wants to merge 11 commits into
Open
Ability to import specific module from Verilog/model from BLIF without making its io the block's IO#398mdko wants to merge 11 commits into
mdko wants to merge 11 commits into
Codecov / codecov/project
succeeded
Aug 13, 2026 in 1s
90.7% (-0.0%) compared to 0e6fdae
View this Pull Request on Codecov
90.7% (-0.0%) compared to 0e6fdae
Details
Codecov Report
❌ Patch coverage is 78.84615% with 11 lines in your changes missing coverage. Please review.
✅ Project coverage is 90.7%. Comparing base (0e6fdae) to head (6461ae9).
| Files with missing lines | Patch % | Lines |
|---|---|---|
| pyrtl/importexport.py | 78.9% | 11 Missing |
Additional details and impacted files
@@ Coverage Diff @@
## development #398 +/- ##
=============================================
- Coverage 90.8% 90.7% -0.0%
=============================================
Files 24 24
Lines 5988 6013 +25
=============================================
+ Hits 5432 5449 +17
- Misses 556 564 +8 ☔ View full report in Codecov by Harness.
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