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Ability to import specific module from Verilog/model from BLIF without making its io the block's IO - #398

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mdko wants to merge 11 commits into
UCSBarchlab:developmentfrom
pllab:submodule-import
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Ability to import specific module from Verilog/model from BLIF without making its io the block's IO#398
mdko wants to merge 11 commits into
UCSBarchlab:developmentfrom
pllab:submodule-import

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@mdko

@mdko mdko commented Jul 9, 2021

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This will import the Verilog module without making its i/o wires the block's i/o wires. Instead, it returns an object whose attributes are input/output wires, accessible via the name of the wires defined on the Verilog module.

Given this Verilog file

module A(x, y, z);
    parameter in_size = 4;
    parameter out_size = 3;
    input [in_size-1:0] x;
    input y;
    output [out_size-1:0] z;

    assign z = x[2:0] & y;
endmodule
# ... possibly more modules

You can import it like so

with open("sample_verilog.v") as f:
    foo = pyrtl.import_from_verilog(f, toplevel="foo", parameters={'in_size': 8, 'out_size': 5}, as_block=False)

foo.x and foo.y are WireVectors, not Input, and they are named with internal names so the module can be imported multiple times without clashes. Similarly, foo.z is WireVector, not Output. All these wires can be connected to others like normal:

i, j = pyrtl.input_list('i/8 j/5')
foo.x <<= i
foo.y <<= j
pyrtl.probe(foo.z, 'out')

The key is the **as_block** parameter you pass to input_from_verilog, which will determine if block-level I/O is created, or instead a "submodule".

This PR also adds support for importing particular models from a BLIF file (since the input_from_verilog() function basically wraps the call to input_from_blif()).

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codecov-commenter commented Jul 9, 2021

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Codecov Report

❌ Patch coverage is 78.84615% with 11 lines in your changes missing coverage. Please review.
✅ Project coverage is 90.7%. Comparing base (0e6fdae) to head (6461ae9).
⚠️ Report is 250 commits behind head on development.

Files with missing lines Patch % Lines
pyrtl/importexport.py 78.9% 11 Missing ⚠️
Additional details and impacted files
@@              Coverage Diff              @@
##           development    #398     +/-   ##
=============================================
- Coverage         90.8%   90.7%   -0.0%     
=============================================
  Files               24      24             
  Lines             5988    6013     +25     
=============================================
+ Hits              5432    5449     +17     
- Misses             556     564      +8     

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3 participants