Add PIC32MZ EF bare-metal wolfIP port: clocks, UART2, wolfCrypt RNG, LAN8740 PHY#140
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Add PIC32MZ EF bare-metal wolfIP port: clocks, UART2, wolfCrypt RNG, LAN8740 PHY#140dgarske wants to merge 2 commits into
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Pull request overview
Adds a new bare-metal PIC32MZ EF architecture port under src/port/pic32mz/, providing early bring-up infrastructure (clocks, UART console, timebase), a wolfCrypt hardware TRNG self-test configuration, and initial Ethernet EMAC MDIO + LAN8740 PHY link bring-up scaffolding.
Changes:
- Introduces PIC32MZ EF device configuration and 200 MHz clock/flash setup, plus a CP0-based millisecond timebase.
- Adds UART2 console support with XC32
printfretargeting and a standalone wolfCrypt RNG self-test usingWOLFSSL_PIC32MZ_RNG. - Adds initial EMAC MII-management (MDIO) routines and a MAC-agnostic LAN8740 PHY bring-up module, with a command-line XC32 Makefile build/flash flow.
Reviewed changes
Copilot reviewed 20 out of 20 changed files in this pull request and generated 4 comments.
Show a summary per file
| File | Description |
|---|---|
| src/port/pic32mz/.gitignore | Ignores XC32/MDB build and flash artifacts for the new port. |
| src/port/pic32mz/Makefile | XC32-based command-line build/flash rules and wolfCrypt source inclusion for self-test. |
| src/port/pic32mz/board.h | Board- and clock-related constants (SYSCLK/PBCLK, UART pins, LEDs). |
| src/port/pic32mz/cache.h | MIPS KSEG address helpers intended for coherent DMA/EMAC access patterns. |
| src/port/pic32mz/clock_init.c | Flash wait-state and prefetch configuration for 200 MHz operation. |
| src/port/pic32mz/clock_init.h | Declares clock/flash init routine for the port. |
| src/port/pic32mz/device_config.c | PIC32MZ DEVCFG0-3 configuration word settings for the target board. |
| src/port/pic32mz/main.c | Bring-up application tying together clock, UART, timebase, RNG self-test, and PHY init. |
| src/port/pic32mz/phy_lan8740.c | LAN8740 PHY scanning/reset/autoneg/link reporting via MDIO function pointers. |
| src/port/pic32mz/phy_lan8740.h | PHY driver API and link-status struct definitions. |
| src/port/pic32mz/pic32mz_eth.c | EMAC module enable/reset and clause-22 MDIO read/write primitives. |
| src/port/pic32mz/pic32mz_eth.h | EMAC/MDIO init and accessor function declarations. |
| src/port/pic32mz/rng_selftest.c | Standalone RNG self-test using wolfCrypt WC_RNG + coarse sanity checks. |
| src/port/pic32mz/rng_selftest.h | Declares the RNG self-test entrypoint. |
| src/port/pic32mz/timebase.c | CP0 Count-derived 64-bit extended counter and millis()/delay_ms(). |
| src/port/pic32mz/timebase.h | Declares millis()/delay_ms() timebase API. |
| src/port/pic32mz/uart_console.c | UART2 init, TX/RX helpers, and XC32 _mon_putc retarget. |
| src/port/pic32mz/uart_console.h | UART console API declarations and usage notes. |
| src/port/pic32mz/user_settings.h | wolfCrypt feature selection for PIC32MZ RNG self-test (trimmed algorithms, no FS/sockets). |
| src/port/pic32mz/wolf_compat.c | wolfCrypt min/max shim functions for the bare-metal environment. |
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…LAN8740 PHY, EMAC/RMII DMA, DHCP, TCP echo
danielinux
requested changes
Jul 16, 2026
Address review feedback on the PIC32MZ EF wolfIP port. device_config.c: correct the FETHIO/EREFCLK comment. It claimed the RMII reference clock defaults to RB4 (RJ11 alternate); the hardware-validated pic32mz_eth.c is authoritative - under FETHIO=ON the default 144-pin I/O set places EREFCLK on RJ11, which pic32mz_eth_init() forces to digital. Reword the comment to match and point at that function. Runtime PHY link recovery. On a link-down startup phy_lan8740_bringup() returns -2 before the speed/duplex read, so the MAC was committed to 10 Mbps half duplex and never revisited: a cable inserted after boot would link at the PHY while the MAC stayed misconfigured, with no recovery short of a reset. Add phy_lan8740_link_status() (a reset-free BMSR/SCSR read, safe to poll on an established link) and pic32mz_eth_link_update(), called once per second from the main heartbeat, which re-applies EMAC1CFG2 / EMAC1IPGT / EMAC1SUPP.SPEEDRMII only on a link change. This fixes both the cable-insert-after-boot case and moving to a 10 Mbps switch. Also factor the SCSR decode into a shared helper, fix the false "-2 yields valid speed/duplex" comments in phy_lan8740.h / pic32mz_eth.c, and reword the startup message now that recovery actually happens.
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Summary
New bare-metal wolfIP port for the Microchip PIC32MZ EF Starter Kit (PIC32MZ2048EFM144, MIPS32 M-class) with a LAN8740 PHY daughter board over RMII. This is a brand-new architecture for wolfIP (first MIPS/PIC32 target) and also verifies wolfCrypt's built-in hardware TRNG (
WOLFSSL_PIC32MZ_RNG). Early bring-up code is factored so a future wolfBoot PIC32MZ port can reuse it. All new code lives undersrc/port/pic32mz/.Features
make,xc32-gcc), matching the other wolfIP ports; no MPLAB X project required. Targets32MZ2048EFM144via the PIC32MZ-EF DFP,-O1(free XC32 tier).device_config.c,clock_init.c): DEVCFG0-3 config words (POSC EC 24 MHz -> SPLL 200 MHz SYSCLK, PBCLK2/PBCLK5 = 100 MHz, RMII selected), flash wait-states and prefetch. Isolated for wolfBoot reuse.uart_console.c): 115200 8N1 on RPB14 (U2TX) / RPG6 (U2RX) with PPS mapping, plus XC32_mon_putcretarget soprintfgoes to the serial console.timebase.c): 64-bitmillis()derived from the CP0 core-timer with software wrap extension; drives the wolfIP poll loop.rng_selftest.c,user_settings.h): exercisesWOLFSSL_PIC32MZ_RNG, generating and sanity-checking random blocks; a failing self-test is treated as fatal. Compiles the needed wolfcrypt sources directly from the sibling wolfssl checkout; keeps the crypto engine hash/AES acceleration off so SHA-256 (DRBG) stays software for this milestone.pic32mz_eth.c): EMAC + RMII + MII-management bring-up, clause-22 MDIO read/write primitives, PBCLK5 / PMD6 module enable before EMAC access, and full RX/TX DMA descriptor rings (coherent/uncached buffers) wired to the wolfIPpoll/senddevice ops.phy_lan8740.c): MAC-agnostic (function-pointer MDIO), scans for the PHY, resets, advertises 10/100 full/half, runs auto-negotiation, and reports resolved link speed/duplex. Distinguishes a non-fatal "link down" result from real MDIO/PHY errors.cache.h): KSEG0/KSEG1 and virtual/physical macros for coherent EMAC descriptor/buffer access.main.c): TRNG self-test, DHCP client, and a TCP echo server on port 7 (or a throughput server on port 9 in theSPEED_TESTbuild). Fatal bring-up failures (RNG, Ethernet, socket setup) halt the board rather than continue in a partial state.make flash): programs the hex via MDB (MPLAB X v6.30), erase-before-program, on the ICSP/debug header; the tool is overridable withMDB=/MDB_TOOL=. (Headlessipecmdcannot resolve device packs; MDB can.)Hardware verification status
Verified on hardware (PIC32MZ EF Starter Kit, LAN8740 over RMII, flashed via MPLAB ICD 5):
RNG self-test: PASS, distinct entropy each boot.