Embedded_Microprocessor_System_Design_using_FPGAs  1. edition

Here is a brief overview of the CD HDL files and the related book chapters.
============================================================
For Altera/Intel Quartus software/ DE boards the following source code should be used:

* ARM (Chapter 11)
  -- DE1_SoC_ TopDown system with 6 example applications

* NiosII (Chapter 9)
  -- DE1_SoC_Basic_Computer with FECG and FMIPS measurments
  -- DE1_SoC_Custom_IP64sqrt with 64 double FP CIP
  -- DE1_SoC_TopDown system with 6 example applications

* Quartus
  -- trisc2 Q15.1 VHDL tiny PicoBlaze model (Chapter 7)
  -- trisc3arm Q15.1 VHDL tiny ARM Cortex-A9 model (Chapter 11)
  -- trisc3mb Q15.1 VHDL tiny MicroBlaze model (Chapter 10)
  -- trisc3nios Q15.1 VHDL tiny Nios II model (Chapter 9)
  -- urisc  Q15.1 VHDL ultimate RISC mode (Chapter 2)

* vQuartus  (Appendix A)
  -- trisc2 Q15.1 Verilog tiny PicoBlaze model
  -- trisc3arm Q15.1 Verilog tiny ARM Cortex-A9 model
  -- trisc3mb Q15.1 Verilog tiny MicroBlaze model
  -- trisc3nios Q15.1 Verilog tiny Nios II model
  -- urisc  Q15.1 Verilog ultimate RISC model

===========================================================
For Xilinx Vivado software/ ZyBo boards the following source code should be used:

* ARM (Chapter 11)
  -- ZyBo_Basic_Computer with FP performance measurements

* MicroBlaze (Chapter 10)
  -- MB_Basic_Computer with FP performance measurements
  -- MB_Basic_Computer_wFPH with FP co-processors
  -- MB_HDMI_CIP with 4 color 4 font HDMI custom IP

* Vivado
  -- trisc2 V2016.4 VHDL tiny PicoBlaze model (Chapter 7)
  -- trisc3arm V2016.4 VHDL tiny ARM Cortex-A9 model (Chapter 11)
  -- trisc3mb V2016.4 VHDL tiny MicroBlaze model (Chapter 10)
  -- trisc3nios V2016.4 VHDL tiny Nios II model (Chapter 9)
  -- urisc  V2016.4 VHDL ultimate RISC model (Chapter 2)


* vVivado  (Appendix A)
  -- trisc2 V2016.4 Verilog tiny PicoBlaze model
  -- trisc3arm V2016.4 Verilog tiny ARM Cortex-A9 model
  -- trisc3mb V2016.4 Verilog tiny MicroBlaze model
  -- trisc3nios V2016.4 Verilog tiny Nios II model
  -- urisc  V2016.4 Verilog ultimate RISC model

For each board separate ZIP files with updated pin assignements and SW examples have been composed.
This list will be updated as new boards become available.

The following boards are supported (price as of 7/2026):
Board        Vendor           ARM      VGA/HDMI   7-segments   SW   LEDs  Price
===============================================================================
DE1-SoC       TerASIC/Intel    Yes       VGA          6        10   10    $377
DE2-115       TerASIC/Intel    No        VGA          8        18   27    $779
DE0-Nano      TerASIC/Intel    No        ---          0        4     8    $108
DE10-Lite     TerASIC/Intel    No        VGA          6        10    10   $140
DE10-Nano     TerASIC/Intel    Yes       HDMI         0        4     8    $225
DE10-Standard TerASIC/Intel    Yes       VGA          6        10   10    $499

ZyBo          Digilent/Xilinx  Yes     VGA+HDMI       0        4     5    $299
PYNQ Z2       TUL/Xilinx       Yes      HDMI          0        2    4+6   $299
ZedBoard      AVNET/Xilinx     Yes     VGA+HDMI       0        8     8    $589