static-timing-analysis--sta

Here are 5 public repositories matching this topic...

Quang-Minh-Phung / DienTu_TKVM_Documents

Kho tài liệu đi từ nền tảng Điện tử căn bản đến Thiết kế vi mạch, tập trung vào Front-End (RTL/DV). Tích hợp kiến thức bổ trợ cho các hướng công việc khác thuộc chuyên ngành Điện Tử. Biên soạn bởi Minh Ú (Phùng Quang Minh).

Updated Aug 10, 2026

MohammedS2lah / STA-Visualizer

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Interactive Static Timing Analysis (STA) visualizer for understanding Setup & Hold timing with live waveforms, timing diagrams, slack equations, skew, jitter, and path analysis.

setup html asic fpga electronics interactive timing eda educational hold computer-architecture vlsi vlsi-physical-design digital-design sta timing-analysis static-timing-analysis vlsi-design static-timing-analysis--sta

Updated Aug 3, 2026
HTML

smit-1301 / sync-fifo-rtl-to-gdsii

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End-to-End ASIC Design of an 8×32 Synchronous FIFO featuring Verilog RTL design, assertion-based verification in Vivado, and RTL-to-GDSII implementation using OpenLane with the SKY130 PDK.

asic verilog systemverilog fifo vlsi klayout digital-design gdsii physical-design rtl-design openlane sky130-pdk static-timing-analysis--sta

Updated Jul 13, 2026
Verilog

avaamar / eda-analyser

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Python tool to automate Quartus STA and synthesis report parsing. Extracts WNS, TNS, and resource utilisation metrics with visual summaries.

python fpga eda quartus imperial-college-london hardware-design static-timing-analysis--sta

Updated Aug 31, 2026
Python

Puji7tha / pipelined-cpu-alu-comparator

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Two-stage 32-bit pipelined CPU in structural Verilog. Adder architecture comparison through the Cadence/Synopsys flow, plus a tree comparator ALU and the verification gap that let a functional bug through.

cpu verification verilog vlsi rtl-design static-timing-analysis--sta

Updated Sep 8, 2026
Verilog

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