Virtual memory address translation simulator with Translation Lookaside Buffer (TLB) cache hit/miss tracking.
Virtual memory address translation simulator with Translation Lookaside Buffer (TLB) cache hit/miss tracking.
MemGPT-inspired tiered memory system with working memory, archival storage, and automated context paging
MemGPT-inspired tiered memory system with working memory, archival storage, and automated context paging
A simple college project to simulate how memory paging works using Chart.js.
Trabajo practico de la Materia Sistemas Operativos de la UTN FRBA
This project simulates a processor's access to memory using a paging mechanism. It involves the implementation of functions to handle memory management, page faults, and page swapping.
Operational System Memory Paging Simulator
Run 35B MoE models on a laptop with only 16 GB of RAM
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