Skip to content

Clear upper vector registers after the LtHash AVX-512 kernels #4164

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
masih merged 2 commits into from
Sep 14, 2026
+30 −4
Merged

Clear upper vector registers after the LtHash AVX-512 kernels #4164

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
ebd5148
Clear upper vector registers after the LtHash AVX-512 kernels
masih Sep 14, 2026
52b4651
Clear upper registers in simdBackend wrappers instead of each kernel
masih Sep 14, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
26 changes: 22 additions & 4 deletions sei-db/state_db/sc/flatkv/lthash/backend_simd_amd64.go
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,11 @@ import (

//go:generate go run gen_blake3_xof16.go

// vzeroupper clears the upper halves of the vector registers.
//
//go:noescape
func vzeroupper()

// simdBackendName is the name reported by ActiveBackend for the AVX-512 path.
const simdBackendName = "simd"

Expand All @@ -22,11 +27,24 @@ func simdBackend() (backend, bool) {
if !archsimd.X86.AVX512() || !archsimd.X86.AVX512VBMI2() {
return backend{}, false
}
// The compiler emits no VZEROUPPER after AVX-512 code, and legacy-SSE code
// in the caller (memmove, SHA-NI) runs several times slower while the upper
// halves are dirty, so every kernel is wrapped here rather than trusting
// each one to clear them.
return backend{
name: simdBackendName,
expand: expandSIMD,
add: addSIMD,
sub: subSIMD,
name: simdBackendName,
expand: func(data []byte, dst *LtHash) {
expandSIMD(data, dst)
vzeroupper()
},
add: func(dst, src *LtHash) {
addSIMD(dst, src)
vzeroupper()
},
sub: func(dst, src *LtHash) {
subSIMD(dst, src)
vzeroupper()
},
}, true
}

Expand Down
8 changes: 8 additions & 0 deletions sei-db/state_db/sc/flatkv/lthash/zeroupper_amd64.s
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
//go:build goexperiment.simd && amd64

#include "textflag.h"

// func vzeroupper()
TEXT ·vzeroupper(SB), NOSPLIT, $0-0
VZEROUPPER
RET
Loading