Harden large CUDA host staging allocations - #19
Conversation
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The wheel built from this head was validated inside the clean r21 inference image on an RTX PRO 6000 Blackwell Server Edition. A 2 GiB mapping registered successfully as one region (0.364 s), and the segmented path registered all 8 x 256 MiB ranges (0.045 s). An AIO_BUFFERED load with |
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The exact PR head The image completed TP2 InstantTensor BUFFERED loading and the full DS4 runtime gate. The original open-driver host from rtx6kpro #52 rejects both whole-region and first-segment registration, so it has been asked to retest r27 specifically to exercise the new runtime-pinned allocation fallback. That external confirmation is still pending and is not being inferred from the validation host. Reproduction and runbook: |
Problem
InstantTensor buffered backends allocate one contiguous host staging buffer and register it with one cudaHostRegister call. At TP2 defaults this is commonly 2 GiB per rank. Some CUDA driver/kernel combinations reject both the single large registration and its segmented retries, so the loader aborts before reading weights even though runtime-allocated pinned memory is available.
Change
No buffer size, io_depth, loading order, or tensor semantics change. Each fallback is entered only after the preceding path fails.
Validation
The original failing NVIDIA 610.43.02 open-kernel host is not locally available. The new final fallback therefore still requires confirmation on that host; it is not claimed as field-validated yet.