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…it(DCC) The DCC is a DMA Engine designed to capture and store data during system crash or software triggers. The DCC operates based on user inputs via the debugfs interface. The user gives addresses as inputs and these addresses are stored in the dcc sram. In case of a system crash or a manual software trigger by the user through the debugfs interface, the dcc captures and stores the values at these addresses. This patch contains the driver which has all the methods pertaining to the debugfs interface, auxiliary functions to support all the four fundamental operations of dcc namely read, write, read/modify/write and loop. The probe method here instantiates all the resources necessary for dcc to operate mainly the dedicated dcc sram where it stores the values. The DCC driver can be used for debugging purposes without going for a reboot since it can perform software triggers as well based on user inputs. Also add the documentation for debugfs entries which explains the functionalities of each debugfs file that has been created for dcc. The following is the justification of using debugfs interface over the other alternatives like sysfs/ioctls i) As can be seen from the debugfs attribute descriptions, some of the debugfs attribute files here contains multiple arguments which needs to be accepted from the user. This goes against the design style of sysfs. ii) The user input patterns have been made simple and convenient in this case with the use of debugfs interface as user doesn't need to shuffle between different files to execute one instruction as was the case on using other alternatives. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
The config file is created to contain specific debug features such as DCC/memory dump driver. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Create qcom-dcc dev driver for matching the qcom-dcc driver without DT. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
The memory dump driver allows various client subsystems to register respective dump regions. At the time of deadlocks or cpu hangs these dump regions are captured to give a snapshot of the system at the time of the crash. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Create memory dump device driver for matching the memory dump v2 driver without DT configuration. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Memory dump driver needs a large CMA memory zone for storing memory dump table. Add codes for reserving CMA memory during the init stage. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add device configuration to enable DCC on Pakala platform. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add memory dump table configuration to enable memory dump function on Pakala platform. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add device configuration to enable DCC on Kaanapali platform. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add memory dump table configuration to enable memory dump function on Kaanapali platform. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add device configuration to enable DCC on Hamoa platform. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add memory dump table configuration to enable memory dump function on Hamoa platform. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Fix the wrong arrary size issue for Talos. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add device configuration to enable DCC on Glymur platform. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Glymur is sharing the same dump table content with Hamoa. So add Glymur's chip IDs for registering the dump table in memory. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Configure the linked list with defined register entries in dcc_probe. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add the registers for configuring the linked_list of the DCC driver for debugging purpose. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…ebug The DCC device stub driver was registered with module_init(), which runs during the initcall sequence before late_initcall(). The DCC hardware depends on resources that are not yet available at that point, causing the driver to fail silently during early boot. Switch to late_initcall() so the driver initialises after all subsystem dependencies are ready. Remove the module_exit() registration since the driver is now built-in only. Update qcom_debug.config to build CONFIG_QCOM_DCC and CONFIG_QCOM_DCC_DEV as built-in (=y) instead of loadable modules (=m) to match the late_initcall() requirement and allow early boot debugging. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…t debug The memory dump device stub driver was registered with module_init(), which runs before late_initcall(). The memory dump subsystem depends on resources that are not yet available at that point, causing the driver to fail silently during early boot. Switch to late_initcall() so the driver initialises after all subsystem dependencies are ready. Remove the module_exit() registration since the driver is now built-in only. Update qcom_debug.config to build CONFIG_QCOM_MEMORY_DUMP_DEV as built-in (=y) instead of a loadable module (=m) to match the late_initcall() requirement and allow early boot debugging. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add the full DCC register capture list for the Lemans platform derived from debug_config_qcs9100.sh. The registers cover LPM, TSENS, PLL, LIMITS, and DDR subsystems, all configured on linked list 6 to match the runtime script (LLNUM=6 in configure_dcc()). Consecutive single-word reads are merged into burst entries (e.g. "R addr N") to keep the array compact; the kernel driver merges them identically via dcc_config_add(). Estimated SRAM usage is ~19 KB, within the 24 KB (0x6000) budget for the Lemans DCC RAM. Move the lemans DCC configuration (entries array, link config, dcc config, and pdata) into a dedicated header qcom-dcc-lemans-config.h to avoid bloating qcom-dcc-dev.c with the large register table. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Move the talos DCC configuration (entries array, link config, dcc config, and pdata) into a dedicated header qcom-dcc-talos-config.h, consistent with the approach used for the lemans config. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
The lemans_pdata is shared by both Lemans (534, 667, 676) and Monaco (606, 674, 675) SoC variants. Add comments to distinguish the two groups and reorder the case labels accordingly. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add the full DCC register capture list for the Kodiak platform derived
from debug_config_qcm6490.sh. The registers are distributed across
three linked lists:
- Link list 6: pcu, epss, pimem, core, gemnoc, tsens, spmi, gpu,
sysnoc, aggrenoc, gcc (430 entries)
- Link list 4: confignoc, limits, gic, mmssnoc, apps_rsc, misc, ddr
(450 entries)
- Link list 3: lpass_rsc, nsp_rsc, sdi_debug, lpass_cdsp_tunning,
wpss_rsc, video_noc (231 entries)
Estimated SRAM usage is ~14 KB, well within the 24 KB (0x6000) budget.
Move the kodiak DCC configuration (entries arrays, link configs, dcc
config, and pdata) into a dedicated header qcom-dcc-kodiak-config.h,
consistent with the approach used for talos and lemans.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add the DCC register capture list for the Pakala platform. The registers are distributed across two linked lists: - Link list 6: 910 entries - Link list 4: 212 entries Estimated SRAM usage is ~15 KB, within the 16 KB (0x4000) budget. Move the pakala DCC configuration (entries arrays, link configs, dcc config, and pdata) into a dedicated header qcom-dcc-pakala-config.h, consistent with the approach used for other platforms. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add the DCC register capture list for the Shikra platform (SoC IDs 756, 758, 759) across two linked lists and move the configuration into a dedicated header qcom-dcc-shikra-config.h. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add memory dump table configuration to enable memory dump function on Shikra platform. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Glymur was reusing Hamoa's dump table, but its IMEM base address differs. Add a dedicated dump table for Glymur with the correct imem_base and register it under Glymur's chip IDs. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add C800-C1100 context dump items to Hamoa's dump table to cover CPU8-CPU11, and bump the ETR/ETFSWAO register dump sizes to match. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Glymur was reusing Hamoa's dump table, but it has additional CPUs. Add a dedicated Glymur dump table with Hamoa's items plus C1200-C1700 context entries to cover CPU12-CPU17. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Replace the SPR_DUMP_CPU1-CPU7 macros with SPR_DUMP_CPU11 and update the range check in mem_dump_alloc() so SPR dump initialization covers CPU0-CPU11 instead of stopping at CPU7. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add per-CPU SPR context, per-CPU and per-cluster cache dump entries, a combined CPU context entry, and the CPUSS_REG dump item to Hamoa's dump table to cover CPU0-CPU11. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add per-CPU SPR context, per-CPU and per-cluster cache dump entries, a combined CPU context entry, and the CPUSS_REG dump item to Glymur's dump table to cover CPU0-CPU11. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…non-secure world Add assign_dump_table_region() to notify TZ that the memory dump table region should be made accessible to AOP, via a self-contained SCM SMC call (QCOM_SCM_SVC_UTIL / QCOM_SCM_UTIL_DUMP_TABLE_ASSIGN). The SMC convention probe (__get_convention()) and dispatch helper are kept local to this driver rather than exported from qcom_scm, since only the register-argument SMC path is needed here. Wire it into mem_dump_alloc(), falling back to the IMEM-based dump table registration path if the SCM call fails. signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
MAX_CORE_NUM bounds the sprdata[] array and the SPR CPU index checks in mem_dump_alloc()/spr_config_store(). It was still set to 8 even though the SPR dump range was already extended to cover CPU0-CPU11. Bump it to 12 so all cores are accounted for. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…ation Remove the CACHE_CLUSTER0-2 dump entries from Hamoa's and Glymur's dump tables; the per-cluster cache dump is redundant with the existing per-CPU CACHE_CPU0-11 entries and pushed the table size well past the reserved CMA pool. Grow the memdump CMA reservation from 0x3000000 to 0x5000000 so it covers the largest dump table (Hamoa/Glymur, now ~56MB with per-CPU SPR/cache entries for CPU0-CPU11) with headroom. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add the memory dump table for the Nord platform (SoC IDs 648, 690, 691, 692, 798, 803), including new CPUSS cluster/per-CPU and GPU scandump entries in the dump_ids enum. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add the DCC register capture list for the Nord platform (SoC IDs 648, 690, 691, 692, 798, 803) in a dedicated header qcom-dcc-nord-config.h and enable DCC support for it. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
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Merge changes to enable debug features.