RFC-0036: Zero-GC 64-Byte Cache-Aligned Flat Arena (Aventine Labs LLC) - #110
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Signed-off-by: Mark Gilbert (@markbgilbert) <mbgilbert@gmail.com> Co-authored-by: Aventine Systems Engineering <contact@aventinelabs.com>
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Update: Dual-OS 60-Minute Training Soak Receipts (Windows 11 vs. Ubuntu 24.04 LTS) & 92/100 Hardware Verification ScorecardTo address enterprise reviewer feedback regarding multi-hour stability and POSIX kernel performance, we have updated RFC-0036 with physical empirical telemetry from continuous 60-minute training runs on physical hardware (AMD Ryzen 9 9955HX Zen 5 + NVIDIA GeForce RTX 5060 Laptop GPU):
Full reproducible code, raw CSV time-series, and standalone C kernels are available in the public benchmark repository: https://github.com/markbgilbert/aegis-zero-gc-benchmark |
…S matrix, and Meta 95/100 scorecard
… to 92/100 with resolved roadmap
Summary
Authored by Mark Gilbert (@markbgilbert - mbgilbert@gmail.com) and the Systems Engineering team at Aventine Labs LLC.
This RFC proposes an optional zero-runtime-allocation, 64-byte cache-aligned (
alignas(64)) C++20 flat arena memory pattern as a high-throughput host-side buffer backend for speculative decoding verification, tensor ingestion, and in-band telemetry in PyTorch runtimes (torch.compileInductor / ExecuTorch).Motivation & Empirical Findings
In modern high-concurrency LLM serving (e.g., Llama 3 / frontier reasoning models), host-side speculative decoding verification is frequently bottlenecked by dynamic memory allocations (
new,malloc,std::vectorresizes) on the CPU host.Our latest empirical benchmarks across physical hardware (AMD Zen 5 & NVIDIA RTX 5060 Blackwell) demonstrate:
-O3 -mavx2) executes at 3.61 Billion ops/sec (0.69 cycles/op measured via hardwarerdtsc).Standalone Benchmark & Reproduction Harness
A standalone reproduction repository with pre-compiled native binaries, C headers, and turnkey Python benchmark scripts is available for maintainer testing at:
https://github.com/markbgilbert/aegis-zero-gc-benchmark