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Pull requests: llvm/circt

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Pull requests list

Pin nanobind to <3 in PyCDE requirements to fix CMake configure failure
#11047 opened Aug 24, 2026 by Copilot AI Loading…
@teqdruid
2
[FIRRTL][SeqToSV] Connect all-ones mask for unmasked ports on masked memories
#11046 opened Aug 24, 2026 by elipsitz Loading…
1
[CI] Enable expensive pattern API checks in nightly integration tests.
#11045 opened Aug 24, 2026 by uenoku Member Loading…
3
[ImportVerilog] Support enum next, prev, name methods ImportVerilog
#11042 opened Aug 21, 2026 by fabianschuiki Contributor Loading…
5
[datapath] Lower Product of Sum to a Booth Encoded Partial Product Array
#11039 opened Aug 21, 2026 by cowardsa Contributor Loading…
2
[OM] Avoid full module verification in release builds
#11037 opened Aug 20, 2026 by uenoku Member Loading…
4
[ImportVerilog] Fix lvalue conversion for output/inout/ref arguments ImportVerilog
#11033 opened Aug 19, 2026 by fabianschuiki Contributor • 3/3 Loading…
3
[LLHD][Mem2Reg] Finer-grained promotion slots
#11018 opened Aug 18, 2026 by AlviseDeFaveri Contributor Loading…
[ESI] Add a pipelined grant scheduler to ChannelArbiter ESI
#11013 opened Aug 18, 2026 by teqdruid Contributor • 3/3 • Draft
19
[HW][Sim] Add SimulationVariableTypeInterface to let hw.inout hold sim value types
#10997 opened Aug 15, 2026 by okekayode Contributor Loading…
3
[Sim] Add sim.assoc_array.clear op Simulator Involving the Sim dialect or other simulation concerns
#10996 opened Aug 15, 2026 by okekayode Contributor Loading…
8
[AXI4] Add xbar op
#10991 opened Aug 14, 2026 by TaoBi22 Contributor • 6/6 Loading…
2
[ImportVerilog] Save the source text of the assert/assume/cover statements.
#10990 opened Aug 14, 2026 by hovhannes-96 Contributor Loading…
1
[BMC] Accept SystemVerilog input
#10983 opened Aug 12, 2026 by 5iri Contributor Loading…
15
[HW] Support struct_inject, struct_explode, and single-field struct_create in HWAggregateToComb
#10981 opened Aug 12, 2026 by jpienaar Member Loading…
10
[FIRRTL] Prototype Registry type and domain register statement
#10940 opened Aug 4, 2026 by uenoku Member • Draft
6
[FIRRTL][ExportVerilog] add ltl.clocked_atom emission
#10906 opened Jul 26, 2026 by Clo91eaf Contributor Loading…
14
[FIRRTL] Fix stale const types in cat/mux canonicalize
#10905 opened Jul 25, 2026 by AayushMainali-Github Contributor Loading…
3 tasks done
1
1
[Affine][ToLoopSchedule] Materialize forwarding-only stages
#10893 opened Jul 23, 2026 by takatodo Loading…
1
[CombFolds] Fix self loop in extract(concat) cannonicalization
#10892 opened Jul 23, 2026 by uenoku Member • Draft
1
3
[FIRRTL][Seq] Add explicit clock edge
#10879 opened Jul 21, 2026 by Clo91eaf Contributor Loading…
33
[ImportVerilog] Support $past(expr, number_of_tick) and error explicitly on unhandled sampled-value arities
#10868 opened Jul 20, 2026 by VecoMr Member Loading…
8
[ImportVerilog] Support %p format specifier for int, string, and struct
#10865 opened Jul 20, 2026 by VecoMr Member Loading…
2
[FIRRTL] Support constants in InferDomains
#10837 opened Jul 16, 2026 by seldridge Member • Draft
1
[FIRRTL] Generalize walkDrivers
#10836 opened Jul 16, 2026 by seldridge Member Loading…
1
ProTip! Updated in the last three days: updated:>2026-08-21.