Qualify post-v0.2 upstream changes with context ABI and FP8 CPU safety checks #20

Triage

P2 / enhancement / owner qualification. The FP8 report is upstream-confirmed; exposure of our pinned artifact is NOT established.

Current layers — 2026-10-21

• Published owner v0.2.0-4, owner c9922d960c79f7ba7381161ca6784f3b7c1e2fce, retains upstream 3f8527a46c54ecf4cb4ed6003da8e8982283c73c. The manifest bytes verify SHA-256 58f2aa7f89cdffd9f28097b47eb58750f7c24f94bf1f2fc92118a9bbe3375d4b. Public core 0.15.5, current main and SD companion 0.15.2 retain this artifact. Metal: a failed GPU command buffer still returns an image as success #19's Metal fail-loud guard is delivered, not physical-watchdog prevention.
• Raw main/release master-982-0518b34 is 0518b34374761cb82aeda5ad3c2f0686fdad2cec: 53 commits beyond bundled source, five since the previous scan. Exact-head CI succeeds. No newer owner artifact or automatic pin bump.
• New raw changes are runtime-quantized CLI LoRA auto-application #2162, server sigma defaults #2172, server reference-edit routing/new capability export #2167, and server recipes/loading/job timestamps #2176. These are not new image families or automatically public Dart LoRA/sigma/edit features.
• The exact header delta includes batched_cfg, two context-mode pointers, preview/ref-conditioning exports and two extra convert_with_components parameters. Audit sizes/offsets/defaults/signatures and guarded wrappers, then regenerate bindings/capabilities; a pin-only update is unsafe.
• New-family/derivative coverage remains raw-only: Iris-3B and Z-Image L2P use pixel-space/no-VAE recipes; FLUX.3 (#1130) needs its FLUX.2 VAE/Qwen3-VL components; MOSS (#1166) additionally needs external-tokenizer transport. Existing owner umbrella and consumer tickets remain adequate. TAEQI is a component, MoSR (#1069) an upscaler, Qwen Turbo (#1070) a schedule variant; no new family landed in today's delta.
• FP8 #2139 is fixed by #2140, first master-966; conv throughput #2137 by #2141, first master-967. Pinned exposure/consumer delivery remain unproven. New #2173 reports an RDNA3 probe false-negative with identical forced/default pixels and similar timing, not proven recurrence of #2137. Metal #2149, Krea2 AMD #2154, video #1976 and ESRGAN #2163 remain open; #2166 and draft #2171 are still unmerged.
• New open video reference transport #2177 and StarNodes INT8 metadata #2178 are proposals, not delivered support. BRIA Fibo2 #2179 is only a request. Long-running video/upscaler ownership wrappers remain prerequisites (#1220/#1069); software Vulkan fallback does not qualify hardware GPUs.
• Current-artifact Fix legacy PyTorch checkpoint scanning above 2 GiB #23 remains confirmed: draft #25 adds regression tests with an expected failure, not a source fix. Investigate large PyTorch ZIP checkpoint load timeouts #24 remains open; #922 reports later non-reproduction, which does not reconcile the original large-ZIP timeout or prove a fix. Core #1218 retains the format qualification boundary.

Evidence and benefit

Our v0.2.0-3 manifest pins 3f8527a46c54ecf4cb4ed6003da8e8982283c73c (ggml 89c4413f). Raw main on 2026-10-15 was 120e3e875c5501c1babb50c0966122cb569d12d4 (ggml d25b121c).

• Flash Attention and convolution mode updates append flash_attn_mode and conv_direct_mode pointers to sd_ctx_params_t: feat: add per-module automatic flash attention selection leejet/stable-diffusion.cpp#2132 and feat: add automatic direct convolution selection leejet/stable-diffusion.cpp#2134
• Wrapped iGPU memory reclamation: fix: reclaim before accepting wrapped Vulkan iGPU memory estimates leejet/stable-diffusion.cpp#2124 (60423ab5; first raw release master-961-60423ab). Broader upstream #2022 remains open.
• FP8 E4M3 CPU report #2139 now has merged repair #2140: 2891378bb17dbed110b391f9aab47d241413153d, first raw release master-966-2891378. CPU matmul falls back from FP8; pinned-artifact exposure still requires reproduction.
• Vulkan auto-convolution slowdown #2137 has merged repair #2141: e47426c04460827e698b6f88ec6431a2007d5c27, first master-967-e47426c. Qualify end-to-end output and timing, not only the probe.
• Historical 2026-10-16 raw head/release was 8cd731e7b4667eb8f40a153315b9a7125d09a58d / master-968-8cd731e: FLUX.3 Image Klein and Klein Base join Iris-3B and Z-Image L2P. MoSR is an upscaler, TAEQI2.1 an autoencoder, and Qwen Image 2.1 Turbo a schedule variant. None is added by unchanged published v0.2.0-3. Consumer recipes are tracked in llamadart#1130; #1069/#1070 in llamadart retain their separate scope.

New raw evidence — 2026-10-17

Current raw main/release: f0aac524d3f29140e60ba78f3cfb16d6acea87db / master-973-f0aac52. Owner, current main and published core 0.14.0 still pin v0.2.0-3 / 3f8527a46c54ecf4cb4ed6003da8e8982283c73c.

• Windows UTF-8 model/CLI paths are now merged in #2144 (8c442fb0, first master-969) / #2145 (2f016e8e, first master-970). They remain absent from the owner artifact; test model and auxiliary/output paths separately.
• #2148, 68285df3, adds MOSS-Image Base/SFT, Qwen3.5 encoder and external tokenizer requirements. Consumer llamadart#1166 owns distinct tokenizer/recipe work. Iris, Z-Image L2P and FLUX.3 remain raw-only too.
• #2149 independently isolates Metal GROUP_NORM leaving batch items after the first unwritten in official master-968/969 libraries (CPU controls pass); batched CFG then returns white images. This is an upstream-reported candidate correctness gate, not proof our older pinned artifact is affected, and not the same mechanism as owner Metal: a failed GPU command buffer still returns an image as success #19's command-buffer failure.
• #2147 refreshes ggml/removes conv1d workarounds. Latest raw CI succeeds after the earlier MUSA container failure; successful packaging is not model correctness evidence.

Additional acceptance: model-free asymmetric GROUP_NORM batch-1/batch-2 sentinels plus real-image batched/unbatched CFG controls on the exact candidate and pinned owner Metal library; fail closed or retain a supported unbatched route if affected. Cover MOSS tokenizer/FLUX.2 VAE loading (#2150 report lacks full logs) and Windows non-ASCII paths. Preserve SD#19 at P1 independent of mitigations or missing hardware.

Acceptance

• Select an exact candidate; audit wrapper exports and struct sizes/offsets/default initialization. An appended pointer changes FFI layout; a pin-only update with old bindings is not acceptable.
• Reproduce or explicitly bound FP8 CPU exposure on the pinned artifact and candidate. Add positive and negative controls ensuring fallback or an actionable refusal, never a process crash. Do not label current llamadart affected without evidence.
• Preserve explicit on/off behavior when adopting auto modes; qualify CPU/Metal/Vulkan, mixed-device decisions, memory pressure, logs, cancellation and error-state recovery. Retain existing iOS direct-VAE refusal unless independently fixed.
• Validate representative new families/components and reject unsupported weight variants; link consumer API work rather than claiming native support equals Dart support.
• Produce digest/provenance-verified platform bundles, exports, Apple XCFramework minimum-OS/privacy/signing checks, then coordinate generated bindings, pins, request/capability mapping, docs and examples.
• Keep existing owner Metal: a failed GPU command buffer still returns an image as success #19 and upstream video/VAE/HIP problems separate unless the exact candidate demonstrably fixes them.

Boundaries

Tracking/qualification only. This issue does not authorize publication, workflow dispatch, paid hardware runs, downstream pin changes, or weakening supported-channel policy. No PR-caused regression is alleged without a causal reproduction. Preserve immutable historical artifacts and record unavailable models/hardware explicitly; CPU/software fallback is not hardware GPU qualification.