feat(website): a Chip tab — the datapath each spec declares, and its silicon record

[gHashTag]

Adds a Chip tab to the Spec Explorer: every .t27 spec is drawn as the
datapath it declares, and the formats that have been through the AX7203 carry
their hardware evidence chain beside the drawing.

Three new files plus five small edits to SpecExplorer.tsx. Nothing else moves.

The schematic

Derived from declarations the language already forces you to write — the bit
width of every constant, the field layout of every packed struct, the parameter
and return widths of every function. Buses render as parallel lanes with a
travelling pulse; the animation is pausable.

It is deliberately not presented as a netlist. The .t27 → Verilog backend
emits module shells today: 361 of 676 specs produce Verilog yosys accepts, and
every one yields 0 LUTs and 0 flip-flops. There is no placement to draw, and the
panel says so rather than drawing something suggestive.

Rows are capped at 12. The SVG scales to the panel width, so a 53-function spec
such as specs/numeric/gf16.t27 would otherwise shrink every label past reading;
the remainder is counted in words instead of rendered illegibly.

The hardware history

Keyed by an explicit spec-path table, never by name similarity — a spec
cannot acquire a hardware claim by resembling one.

gf4 gf8 gf12 gf16 gf20 gf24	ADD and MUL measured on silicon
SUB	"bitstream ready, not yet flashed" — shown as preparation, not as a result
everything else, incl. gf32	"No hardware run", stated outright

Each claim displays at the strength it was earned: declared / proven by SAT /
bitstream ready / on silicon. Figures are transcribed from
research/goldenfloat-hw-conformance/GOLDENFLOAT_HW_CONFORMANCE_v0.2.md and the
evidence chain it cites — CI run, bitstream SHA-256, JTAG flash, UART log. The
GF16 and GF20 case studies are included, because what the hardware caught that
simulation missed is the most useful thing on the panel.

The section states explicitly that those silicon results belong to hand-written
RTL of the same format, not to the Verilog these specs compile to. The spec and
the core describe the same number format; they are not the same artifact.

Why this is separate from #953

That branch is 16 commits and 787 changed files and conflicts with main — one
add/add conflict on SpecExplorer.tsx, which was added independently on both
sides. The two versions are content-identical apart from this chip work and a
RUN → GO rename, so the feature needs none of the other 786 files. The rename
is left out here as unrelated scope.

Verified

• tsc -b --force — zero errors naming any of the four files; repo baseline is
  179 pre-existing errors, unchanged
• Production build green, and ON THE CHIP confirmed present in the emitted
  SpecExplorer chunk
• Rendered and read back in a browser: specs/numeric/gf16.t27 shows ADD 512/512
  and MUL 512/512 on silicon with the NaN-fix note and the four-link chain; a
  tutorial spec shows "No hardware run"

EN and RU copy for every new string.