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claw: recipes table AF4 round 1 -- two verified fpga-build rows - #9296
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…-baseline-raise, physics-move) Harvest pass #9285: the night loop ran and verified two fpga-build heals this week; both land as rows, keyed to the real stem. - elab-baseline-raise (#9212): iverilog error class documented as emitter debt ("Enable of unknown task") -> check_elab_ratchet.py --update-baseline records the module at its measured count plus 0-error siblings in the same commit. COND holds the line: a NEW error class is reported, never baselined. - physics-move (#9233): real-typed f64 math specs under specs/fpga that yosys rejects at "function real" -> move to specs/physics, re-seal on the lab, re-path suite_expectations by line surgery. Integer-logic siblings stay. Table 19 -> 21 rows; census C_AUTO 15 / C_REVIEW 3 / C_OWNER 3; fpga-build carries 2 rows (one workflow, two checks, different repairs); index pins for rows 19-20; census/gate-count/routing/tool tests updated in the same commit. Lab: typecheck OK, 11/11 tests, 0 FAIL, 0 vacuous. No new duplicate groups. Refs #9285, #9281. Part of #9271. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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…(slices_equal, starts_with) (#9299) Fresh master dbf1920 re-scan first (recipe row dupe-bless, specs/claw/recipes.t27): exactly the two known 2x groups, nothing new -- engine.t27 (#9292), the recipes table rounds (#9296/#9297) and the gates regen added no unledgered bodies. Port wave quiet since #9275 (2026-10-12 16:20Z, >26 h). 712 bodies / 212 groups / 2003 specs; 199 -> 201 blessed groups, two scoped lines added, rescan clean. Refs #9281. Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
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AF4 round 1 (#9285): harvest verified recipes into the table. Two fpga-build heals the night loop actually ran and merged this week become rows, keyed to the real stem.
The two rows
Enable of unknown taskerror, a class the tool's docstring already documents as emitter debt (yosys/Vivado accept, iverilog refuses). Repair:check_elab_ratchet.py --update-baselinerecords the module at its measured count, and the six 0-error siblings get rows in the same commit. The COND is the guardrail: a NEW error class is reported, never baselined.specs/fpga/; yosys parse-rejectsfunction realon principle (iverilog accepts, which is why elaboration said 0). Repair: move tospecs/physics/, re-seal on the lab, re-pathsuite_expectations.jsonby line surgery, re-run the corpus ratchets. Integer-logic siblings (secded) stay where they are.Both C_AUTO: agent-executed end to end, verified by the gates they heal, auto-merged.
Table shape
21 rows; census C_AUTO 15 / C_REVIEW 3 / C_OWNER 3;
fpga-buildcarries 2 rows (one workflow, two checks, different repairs -- the stem join allows exactly this). Index pins extended to rows 19-20; census, gate-count, routing and instrument tests updated in the same commit (the table cannot drift silently).Verification
Lab: typecheck OK (0 errors), 11/11 tests, 0 FAIL, 0 vacuous. ASCII clean.
dupe_scan --like: no new groups (str_eq 2 already in the ledger from #9290).Refs #9285, #9281; part of #9271. Next harvest rounds: trinity/trios/fpga CI patterns (the related-repos pass) and the lean-completeness family.
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