fpga: the bench board is an ALINX AX7203, and a t27 Ethernet beacon for it (Closes #7788) by gHashTag · Pull Request #7802 · gHashTag/t27

gHashTag · 2026-10-08T12:07:06Z

The board is an ALINX AX7203

A USB camera on the bench read "ALINX" off the PCB. The AX7203 gf8 bitstream from gHashTag/trinity-fpga then answered HW RESULT: 512/512 bit-exact (fails=0) over the AX7203 UART, clocked from the AX7203 oscillator on R4/T4. Our notes had called the board a QMTech Wukong (xc7a200tfgg676). It is xc7a200tfbg484-2: the same die, so IDCODE 0x3636093 never told them apart.

JTAG-only verdicts stand, because those designs touch no package pin.
Pin-level probes written for the Wukong read the wrong pins.
fpga/HARDWARE_SSOT.md gets a dated section with the evidence and the AX7203 pins. CLAUDE.md points at it.

Specs

specs/fpga/eth_beacon.t27 (module EthBeacon). Sends one UDP broadcast, T27E plus a frame counter, every 2^24 cycles at 125 MHz on both KSZ9031 PHYs. It also:
- holds the PHY reset;
- shows the RGMII in-band link and speed of each PHY on the LEDs, with a heartbeat;
- builds the frame for 125 MHz.
- 9/9 tests, 0 vacuous.
specs/fpga/rgmii_sniff.t27 (module RgmiiSniff). Counts frames, in-band status and the frame head in a PHY's receive clock domain. Read over JTAG, it found the link: PHY 2, 1000 Mb/s, full duplex. 3/3 tests.
Both are sealed.

Silicon, 2026-10-08

Timing: post-route 179.69 MHz against a 125 MHz requirement on xc7a200tfbg484-2. Earlier versions reached 64.2 and then 94.6 MHz before the frame was rebuilt as a flat table.
A Mac on the same LAN received the board's datagrams from 192.168.1.227: 816 of 932 and 110 of 119 frames. It was on Wi-Fi, where broadcast is not retransmitted.
Frames arrived at 7.45 per second, which is 125 MHz / 2^24.
The OS accepted every frame it received, so the FCS, the IPv4 checksum and the UDP header are right.
The camera shows the PHY 2 link and gigabit LEDs lit and the heartbeat blinking.

Follows in this PR

The wrapper fpga/verilog/eth_beacon_top.v (IBUFDS, PLLE2_ADV, BUFG, ODDR; 40 lines) and eth_beacon_top.xdc (34 lines). They are pushed after their owner-approved exception, #7794, is on master, because the local hook reads that list from origin/master.

Not done

t27c silicon still targets fbg676. The fbg484 flow was run by hand: yosys, nextpnr-xilinx with the fbg484 chipdb, fasm2frames and xc7frames2bit.
The beacon only transmits: no ARP, no ping.
Loss has not been measured on a wired receiver.

🤖 Generated with Claude Code

…or it (Closes #7788) A USB camera on the bench read "ALINX" off the PCB on 2026-10-08. The board our notes called a QMTech Wukong (xc7a200tfgg676) is an ALINX AX7203 (xc7a200tfbg484-2): the same die, so IDCODE 0x3636093 never told them apart. The AX7203 gf8 bitstream from gHashTag/trinity-fpga answered HW RESULT: 512/512 bit-exact over the AX7203 UART (N15, 160000 baud), clocked from R4/T4. Every JTAG-only verdict stands (those designs touch no package pin); every pin-level probe written for the Wukong read the wrong pins. fpga/HARDWARE_SSOT.md gets a dated section with the evidence and the AX7203 pins, and CLAUDE.md points at it. specs/fpga/eth_beacon.t27 (module EthBeacon, was WukongEthBeacon): one UDP broadcast 192.168.1.227 -> 192.168.1.255:27027 ("T27E" + frame counter) every 2^24 cycles at 125 MHz, on both KSZ9031 PHYs. New for the AX7203: the PHY reset held 2^21 cycles; RGMII in-band status (link, speed) of both PHYs and a frame heartbeat on the four user LEDs, so the camera reads the link; and a frame built for 125 MHz -- an 8-bit position, the next byte fetched a clock ahead into a register the CRC reads, and frame_byte as a table on the absolute position with no index arithmetic. Post-route on xc7a200tfbg484-2: 64.2 MHz with 32-bit index arithmetic, 94.6 with the prefetch, 179.7 with the flat table (the FCS test held the bytes fixed through every rewrite). t27c test-report: 9/9, 0 vacuous. specs/fpga/rgmii_sniff.t27 (module RgmiiSniff): frames, in-band status and the first eight nibbles of the latest frame, counted in a PHY's receive clock domain. Read over JTAG USER3 it found the link: PHY 1 RXC 25 MHz and nothing, PHY 2 RXC 125 MHz, in-band 0xD (link, 1000 Mb/s, full duplex), preamble 0x55555555. 3/3 tests. On silicon, 2026-10-08: the Mac at 192.168.1.29 received the board's T27E datagrams from 192.168.1.227, 816 of 932 and 110 of 119 frames (over Wi-Fi, where broadcast is never retransmitted), at 7.45 frames/s = 125 MHz / 2^24. The camera shows PHY 2 link and gigabit lit and the heartbeat blinking. The wrapper (IBUFDS, PLLE2_ADV, BUFG, ODDR; 40 lines) and the XDC (34 lines) follow in the next commit, once their owner-approved exception (#7794) is on master. Closes #7788 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

#7788) fpga/verilog/eth_beacon_top.v (40 lines, owner-approved-foreign, #7794 on master): IBUFDS for the 200 MHz oscillator on R4/T4, PLLE2_ADV for 125 MHz and a 90-degree copy, two BUFG, and ODDR cells that put each byte of specs/fpga/eth_beacon.t27 on RGMII as two nibbles (the high nibble held one byte back, because ODDR takes D2 on the falling edge) and forward the shifted clock as TXC. Both PHYs get the same frames. The user LEDs light on a low output, so the wrapper inverts them. fpga/verilog/eth_beacon_top.xdc (34 lines): the clock, both PHYs' RGMII pins and resets, and the four LEDs, one port per line (nextpnr's XDC reader does not expand [*]), from the ALINX AX7103/AX7203 manual; bank 16 at LVCMOS33. This is the build that ran on 2026-10-08: post-route 179.69 MHz at 125 MHz on xc7a200tfbg484-2, and the Mac received the board's T27E datagrams. Closes #7788 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

github-actions · 2026-10-08T12:27:44Z

PR Dashboard

Generated at: 2026-10-08 12:27:36 UTC

t27b: @divTrunc and a @panic statement as the reference runs them, from builtin_plan.t27 (Closes #7790) #7808 t27b: @divTrunc and a @panic statement as the reference runs them, from builtin_plan.t27 (Closes #7790) | Created: 2026-10-08 | Updated: 2026-10-08 | 29 failing / 32 total
fpga: the bench board is an ALINX AX7203, and a t27 Ethernet beacon for it (Closes #7788) #7802 fpga: the bench board is an ALINX AX7203, and a t27 Ethernet beacon for it (Closes #7788) | Created: 2026-10-08 | Updated: 2026-10-08 | 26 failing / 28 total
t27b: undefined as an argument the callee never reads is passed, as in the reference, and refused by name where it is read (Closes #7796) #7801 t27b: undefined as an argument the callee never reads is passed, as in the reference, and refused by name where it is read (Closes #7796) | Created: 2026-10-08 | Updated: 2026-10-08 | 22 failing / 37 total
spec(queen): the event log as a bus, a cursor that loses nothing (Closes #7789) #7800 spec(queen): the event log as a bus, a cursor that loses nothing (Closes #7789) | Created: 2026-10-08 | Updated: 2026-10-08 | 29 failing / 30 total
specs(basics): the 27 t27-basics course lessons, upstreamed from trinity's vendored copy (Closes #7793) #7799 specs(basics): the 27 t27-basics course lessons, upstreamed from trinity's vendored copy (Closes #7793) | Created: 2026-10-08 | Updated: 2026-10-08 | 27 failing / 30 total
Port bootstrap/src/compiler.rs lines 23970-24090 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/return_unsized #7797 Port bootstrap/src/compiler.rs lines 23970-24090 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/return_unsized | Created: 2026-10-08 | Updated: 2026-10-08 | 7 failing / 28 total
Port gHashTag/trios:crates/trios-cli/src/cmd/issue.rs (Rust, 2 functions) to specs/port/trios/crates/trios-cli/src/cmd/i #7795 Port gHashTag/trios:crates/trios-cli/src/cmd/issue.rs (Rust, 2 functions) to specs/port/trios/crates/trios-cli/src/cmd/i | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
t27b: a write through an array literal printed @constCast(&[_]E{ ... }) is refused by name, not encoded, from a t27 plan (Closes #7765) #7786 t27b: a write through an array literal printed @constCast(&[_]E{ ... }) is refused by name, not encoded, from a t27 plan (Closes #7765) | Created: 2026-10-08 | Updated: 2026-10-08 | 5 failing / 41 total
Port gHashTag/trios:crates/trinity_loss/src/lib.rs (Rust, 5 functions) to specs/port/trios/crates/trinity_loss/src/lib.t #7760 Port gHashTag/trios:crates/trinity_loss/src/lib.rs (Rust, 5 functions) to specs/port/trios/crates/trinity_loss/src/lib.t | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 31 total
t27b: ?*anyopaque and @ptrFromInt to an optional pointer lower from a t27 plan (Closes #7737) #7744 t27b: ?*anyopaque and @ptrFromInt to an optional pointer lower from a t27 plan (Closes #7737) | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 39 total
t27b: .{} takes its result type, and a store of the fn's own frame address is refused, from t27 plans (Closes #7735) #7743 t27b: .{} takes its result type, and a store of the fn's own frame address is refused, from t27 plans (Closes #7735) | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 39 total
Port gHashTag/trinity:fpga/gf16-pipelined/gf16_dot4_p.v (Verilog, 1 module) to specs/port/trinity/fpga/gf16-pipelined/gf #7734 Port gHashTag/trinity:fpga/gf16-pipelined/gf16_dot4_p.v (Verilog, 1 module) to specs/port/trinity/fpga/gf16-pipelined/gf | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 29 total
fpga: systolic wavefront array spec -- matrix multiply as a schedule (for the ai-accelerator course) #7719 fpga: systolic wavefront array spec -- matrix multiply as a schedule (for the ai-accelerator course) | Created: 2026-10-08 | Updated: 2026-10-08 | 5 failing / 37 total
Port scripts/gen_w328.py (Python, 1 function) to specs/port/scripts/gen_w328.t27 #7709 Port scripts/gen_w328.py (Python, 1 function) to specs/port/scripts/gen_w328.t27 | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
Port fpga/verilog/gft_sadd_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_sadd_jtag.t27 #7708 Port fpga/verilog/gft_sadd_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_sadd_jtag.t27 | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 29 total
Port gHashTag/trinity:fpga/openxc7-synth/quantum_bridge_zero.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-sy #7707 Port gHashTag/trinity:fpga/openxc7-synth/quantum_bridge_zero.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-sy | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
Port gHashTag/trinity:src/tri/author_attribution_guard.zig (Zig, 2 functions) to specs/port/trinity/src/tri/author_attri #7689 Port gHashTag/trinity:src/tri/author_attribution_guard.zig (Zig, 2 functions) to specs/port/trinity/src/tri/author_attri | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 29 total
fpga: four specs parse to the end -- gherkin constructs the parser discards, rewritten in-file (Refs #2474, Refs gHashTag/trinity#1484) #7659 fpga: four specs parse to the end -- gherkin constructs the parser discards, rewritten in-file (Refs #2474, Refs gHashTag/trinity#1484) | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 37 total
Port gHashTag/trinity:src/vibeec/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity/src/vibeec/bogatyrs #7644 Port gHashTag/trinity:src/vibeec/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity/src/vibeec/bogatyrs | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
Port gHashTag/trios:crates/trios-mcp/rings/SR-01/src/audits_new.rs (Rust, 4 functions) to specs/port/trios/crates/trios- #7643 Port gHashTag/trios:crates/trios-mcp/rings/SR-01/src/audits_new.rs (Rust, 4 functions) to specs/port/trios/crates/trios- | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
fpga: RGMII timing arithmetic and Ethernet FCS specs (for the buses course) #7626 fpga: RGMII timing arithmetic and Ethernet FCS specs (for the buses course) | Created: 2026-10-07 | Updated: 2026-10-08 | 0 failing / 2 total
Port gHashTag/trinity:src/phi-engine/vibeec_original/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity #7624 Port gHashTag/trinity:src/phi-engine/vibeec_original/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity | Created: 2026-10-07 | Updated: 2026-10-07 | 2 failing / 31 total
Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-05/src/envelope_size_distribution_uniformity.rs (Rust, 1 function) t #7623 Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-05/src/envelope_size_distribution_uniformity.rs (Rust, 1 function) t | Created: 2026-10-07 | Updated: 2026-10-07 | 2 failing / 31 total
Implement the 1 empty function body in specs/test_framework/graph_drift_detection.t27 #7613 Implement the 1 empty function body in specs/test_framework/graph_drift_detection.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 4 failing / 29 total
Port fpga/verilog/gft_dup_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_dup_jtag.t27 #7612 Port fpga/verilog/gft_dup_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_dup_jtag.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 29 total
fpga(cdc): mmcm, reset_sync and mtbf as t27 specs (Closes #7585) #7586 fpga(cdc): mmcm, reset_sync and mtbf as t27 specs (Closes #7585) | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 39 total
Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-04/src/padding_metadata_leak_guard.rs (Rust, 1 function) to specs/po #7582 Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-04/src/padding_metadata_leak_guard.rs (Rust, 1 function) to specs/po | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 29 total
fpga(coverage): line, toggle and FSM coverage as a t27 spec (Closes #7578) #7579 fpga(coverage): line, toggle and FSM coverage as a t27 spec (Closes #7578) | Created: 2026-10-07 | Updated: 2026-10-07 | 4 failing / 37 total
Port scripts/gen_w376.py (Python, 1 function) to specs/port/scripts/gen_w376.t27 #7568 Port scripts/gen_w376.py (Python, 1 function) to specs/port/scripts/gen_w376.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 29 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/db/queen-pool.ts (TypeScript, 3 functions) to specs/port/ #7567 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/db/queen-pool.ts (TypeScript, 3 functions) to specs/port/ | Created: 2026-10-07 | Updated: 2026-10-07 | 4 failing / 29 total
ci: test only the specs a change can affect -- t27c use-edges feeds specs/ci/affected.t27 (Closes #7565) #7566 ci: test only the specs a change can affect -- t27c use-edges feeds specs/ci/affected.t27 (Closes #7565) | Created: 2026-10-07 | Updated: 2026-10-08 | 4 failing / 40 total
Port scripts/gen_w369.py (Python, 1 function) to specs/port/scripts/gen_w369.t27 #7555 Port scripts/gen_w369.py (Python, 1 function) to specs/port/scripts/gen_w369.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 29 total
Port scripts/gen_w372.py (Python, 1 function) to specs/port/scripts/gen_w372.t27 #7554 Port scripts/gen_w372.py (Python, 1 function) to specs/port/scripts/gen_w372.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 4 failing / 29 total
Port gHashTag/trinity:src/depin/swarm_watch.zig (Zig, 2 functions) to specs/port/trinity/src/depin/swarm_watch.t27 #7553 Port gHashTag/trinity:src/depin/swarm_watch.zig (Zig, 2 functions) to specs/port/trinity/src/depin/swarm_watch.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 29 total
Port gHashTag/trios:tools/acm_ae_check/src/main.rs (Rust, 1 function) to specs/port/trios/tools/acm_ae_check/src/main.t2 #7552 Port gHashTag/trios:tools/acm_ae_check/src/main.rs (Rust, 1 function) to specs/port/trios/tools/acm_ae_check/src/main.t2 | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 29 total
Port fpga/verilog/gft_kat_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_kat_jtag.t27 #7540 Port fpga/verilog/gft_kat_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_kat_jtag.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 29 total
Port gHashTag/trios:crates/trios-trainer/src/data.rs (Rust, 7 functions) to specs/port/trios/crates/trios-trainer/src/da #7539 Port gHashTag/trios:crates/trios-trainer/src/data.rs (Rust, 7 functions) to specs/port/trios/crates/trios-trainer/src/da | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 29 total
t27b: which calls lower as the .len field, decided by lencall.t27 (Closes #7524) #7530 t27b: which calls lower as the .len field, decided by lencall.t27 (Closes #7524) | Created: 2026-10-07 | Updated: 2026-10-08 | 2 failing / 40 total
spec(numeric,math): the GoldenFloat lesson specs compile clean and say only true things #7496 spec(numeric,math): the GoldenFloat lesson specs compile clean and say only true things | Created: 2026-10-07 | Updated: 2026-10-08 | 10 failing / 32 total
fix(gen-c): a local nested array is declared as a C matrix (Closes #7441) #7495 fix(gen-c): a local nested array is declared as a C matrix (Closes #7441) | Created: 2026-10-07 | Updated: 2026-10-08 | 6 failing / 41 total
specs(port trios, browseros): unify LockGuard; rename 11 port-only types (Closes #7486) #7491 specs(port trios, browseros): unify LockGuard; rename 11 port-only types (Closes #7486) | Created: 2026-10-07 | Updated: 2026-10-08 | 3 failing / 30 total
specs(port compiler): unify AssembledInstr, LinkSection, LinkedSymbol, HirBoardResources; rename AsmSection, HwType (Closes #7485) #7490 specs(port compiler): unify AssembledInstr, LinkSection, LinkedSymbol, HirBoardResources; rename AsmSection, HwType (Closes #7485) | Created: 2026-10-07 | Updated: 2026-10-08 | 3 failing / 30 total
t27b: module vars that hold a string or start undefined (Closes #7448) #7470 t27b: module vars that hold a string or start undefined (Closes #7448) | Created: 2026-10-07 | Updated: 2026-10-08 | 15 failing / 45 total
t27b: a test local named for a module var (Closes #7668) #7447 t27b: a test local named for a module var (Closes #7668) | Created: 2026-10-07 | Updated: 2026-10-08 | 0 failing / 4 total
t27core: for over one range and switch as a value, byte-identical to gen-c (Closes #7429) #7436 t27core: for over one range and switch as a value, byte-identical to gen-c (Closes #7429) | Created: 2026-10-07 | Updated: 2026-10-07 | 10 failing / 47 total
t27c: refuse a malformed number literal by name, read 0o as octal (Closes #7319, Closes #2645) #7421 t27c: refuse a malformed number literal by name, read 0o as octal (Closes #7319, Closes #2645) | Created: 2026-10-07 | Updated: 2026-10-07 | 14 failing / 43 total
gen-c: run defer at every exit of its block (Closes #7352) #7406 gen-c: run defer at every exit of its block (Closes #7352) | Created: 2026-10-07 | Updated: 2026-10-07 | 36 failing / 42 total
tri: test runs the tests; mutate plant names what a one-line mutant turns red #7400 tri: test runs the tests; mutate plant names what a one-line mutant turns red | Created: 2026-10-07 | Updated: 2026-10-07 | 4 failing / 37 total
t27b: an array length written as a constant expression (Closes #7347) #7382 t27b: an array length written as a constant expression (Closes #7347) | Created: 2026-10-07 | Updated: 2026-10-07 | 12 failing / 42 total
Port scripts/gen_w370.py (Python, 1 function) to specs/port/scripts/gen_w370.t27 #7335 Port scripts/gen_w370.py (Python, 1 function) to specs/port/scripts/gen_w370.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 7 failing / 29 total

Summary

Status	Count
Total Open PRs	50
PRs with Failing Checks	44
PRs with All Checks Green	6
READY	2
FAILING	44
PENDING	0
NO CHECKS YET	0

These columns do not partition: 2 + 44 + 0 + 0 = 46, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

⚠️ STALE -- sha256(compiler.rs)=39fa3908f9fd != manifest seal=87e5cbd3ad94.
The committed NMSE numbers were certified against an older compiler.rs.
Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

github-actions · 2026-10-08T12:40:26Z

PR Dashboard

Generated at: 2026-10-08 12:40:19 UTC

t27b: @bitCast between an integer and a float of one size, @intFromBool, and std.math.nan / isNan / isPositiveInf / isNegativeInf, from t27 plans (Closes #7791) #7818 t27b: @bitCast between an integer and a float of one size, @intFromBool, and std.math.nan / isNan / isPositiveInf / isNegativeInf, from t27 plans (Closes #7791) | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 3 total
verified: R3-3 receipt from die A under t27c 0.5.1 (Closes #7815) #7816 verified: R3-3 receipt from die A under t27c 0.5.1 (Closes #7815) | Created: 2026-10-08 | Updated: 2026-10-08 | 22 failing / 23 total
t27b: @divTrunc and a @panic statement as the reference runs them, from builtin_plan.t27 (Closes #7790) #7808 t27b: @divTrunc and a @panic statement as the reference runs them, from builtin_plan.t27 (Closes #7790) | Created: 2026-10-08 | Updated: 2026-10-08 | 15 failing / 38 total
fpga: the bench board is an ALINX AX7203, and a t27 Ethernet beacon for it (Closes #7788) #7802 fpga: the bench board is an ALINX AX7203, and a t27 Ethernet beacon for it (Closes #7788) | Created: 2026-10-08 | Updated: 2026-10-08 | 25 failing / 28 total
t27b: undefined as an argument the callee never reads is passed, as in the reference, and refused by name where it is read (Closes #7796) #7801 t27b: undefined as an argument the callee never reads is passed, as in the reference, and refused by name where it is read (Closes #7796) | Created: 2026-10-08 | Updated: 2026-10-08 | 28 failing / 29 total
spec(queen): the event log as a bus, a cursor that loses nothing (Closes #7789) #7800 spec(queen): the event log as a bus, a cursor that loses nothing (Closes #7789) | Created: 2026-10-08 | Updated: 2026-10-08 | 25 failing / 28 total
specs(basics): the 27 t27-basics course lessons, upstreamed from trinity's vendored copy (Closes #7793) #7799 specs(basics): the 27 t27-basics course lessons, upstreamed from trinity's vendored copy (Closes #7793) | Created: 2026-10-08 | Updated: 2026-10-08 | 21 failing / 31 total
Port bootstrap/src/compiler.rs lines 23970-24090 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/return_unsized #7797 Port bootstrap/src/compiler.rs lines 23970-24090 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/return_unsized | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 29 total
Port gHashTag/trios:crates/trios-cli/src/cmd/issue.rs (Rust, 2 functions) to specs/port/trios/crates/trios-cli/src/cmd/i #7795 Port gHashTag/trios:crates/trios-cli/src/cmd/issue.rs (Rust, 2 functions) to specs/port/trios/crates/trios-cli/src/cmd/i | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 29 total
t27b: a write through an array literal printed @constCast(&[_]E{ ... }) is refused by name, not encoded, from a t27 plan (Closes #7765) #7786 t27b: a write through an array literal printed @constCast(&[_]E{ ... }) is refused by name, not encoded, from a t27 plan (Closes #7765) | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 42 total
Port gHashTag/trios:crates/trinity_loss/src/lib.rs (Rust, 5 functions) to specs/port/trios/crates/trinity_loss/src/lib.t #7760 Port gHashTag/trios:crates/trinity_loss/src/lib.rs (Rust, 5 functions) to specs/port/trios/crates/trinity_loss/src/lib.t | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 31 total
t27b: ?*anyopaque and @ptrFromInt to an optional pointer lower from a t27 plan (Closes #7737) #7744 t27b: ?*anyopaque and @ptrFromInt to an optional pointer lower from a t27 plan (Closes #7737) | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 39 total
t27b: .{} takes its result type, and a store of the fn's own frame address is refused, from t27 plans (Closes #7735) #7743 t27b: .{} takes its result type, and a store of the fn's own frame address is refused, from t27 plans (Closes #7735) | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 39 total
Port gHashTag/trinity:fpga/gf16-pipelined/gf16_dot4_p.v (Verilog, 1 module) to specs/port/trinity/fpga/gf16-pipelined/gf #7734 Port gHashTag/trinity:fpga/gf16-pipelined/gf16_dot4_p.v (Verilog, 1 module) to specs/port/trinity/fpga/gf16-pipelined/gf | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 29 total
fpga: systolic wavefront array spec -- matrix multiply as a schedule (for the ai-accelerator course) #7719 fpga: systolic wavefront array spec -- matrix multiply as a schedule (for the ai-accelerator course) | Created: 2026-10-08 | Updated: 2026-10-08 | 5 failing / 37 total
Port scripts/gen_w328.py (Python, 1 function) to specs/port/scripts/gen_w328.t27 #7709 Port scripts/gen_w328.py (Python, 1 function) to specs/port/scripts/gen_w328.t27 | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
Port fpga/verilog/gft_sadd_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_sadd_jtag.t27 #7708 Port fpga/verilog/gft_sadd_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_sadd_jtag.t27 | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 29 total
Port gHashTag/trinity:fpga/openxc7-synth/quantum_bridge_zero.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-sy #7707 Port gHashTag/trinity:fpga/openxc7-synth/quantum_bridge_zero.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-sy | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
Port gHashTag/trinity:src/tri/author_attribution_guard.zig (Zig, 2 functions) to specs/port/trinity/src/tri/author_attri #7689 Port gHashTag/trinity:src/tri/author_attribution_guard.zig (Zig, 2 functions) to specs/port/trinity/src/tri/author_attri | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 29 total
fpga: four specs parse to the end -- gherkin constructs the parser discards, rewritten in-file (Refs #2474, Refs gHashTag/trinity#1484) #7659 fpga: four specs parse to the end -- gherkin constructs the parser discards, rewritten in-file (Refs #2474, Refs gHashTag/trinity#1484) | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 37 total
Port gHashTag/trinity:src/vibeec/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity/src/vibeec/bogatyrs #7644 Port gHashTag/trinity:src/vibeec/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity/src/vibeec/bogatyrs | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
Port gHashTag/trios:crates/trios-mcp/rings/SR-01/src/audits_new.rs (Rust, 4 functions) to specs/port/trios/crates/trios- #7643 Port gHashTag/trios:crates/trios-mcp/rings/SR-01/src/audits_new.rs (Rust, 4 functions) to specs/port/trios/crates/trios- | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
fpga: RGMII timing arithmetic and Ethernet FCS specs (for the buses course) #7626 fpga: RGMII timing arithmetic and Ethernet FCS specs (for the buses course) | Created: 2026-10-07 | Updated: 2026-10-08 | 0 failing / 2 total
Port gHashTag/trinity:src/phi-engine/vibeec_original/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity #7624 Port gHashTag/trinity:src/phi-engine/vibeec_original/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity | Created: 2026-10-07 | Updated: 2026-10-07 | 2 failing / 31 total
Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-05/src/envelope_size_distribution_uniformity.rs (Rust, 1 function) t #7623 Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-05/src/envelope_size_distribution_uniformity.rs (Rust, 1 function) t | Created: 2026-10-07 | Updated: 2026-10-07 | 2 failing / 31 total
Implement the 1 empty function body in specs/test_framework/graph_drift_detection.t27 #7613 Implement the 1 empty function body in specs/test_framework/graph_drift_detection.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 4 failing / 29 total
Port fpga/verilog/gft_dup_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_dup_jtag.t27 #7612 Port fpga/verilog/gft_dup_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_dup_jtag.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 29 total
fpga(cdc): mmcm, reset_sync and mtbf as t27 specs (Closes #7585) #7586 fpga(cdc): mmcm, reset_sync and mtbf as t27 specs (Closes #7585) | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 39 total
Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-04/src/padding_metadata_leak_guard.rs (Rust, 1 function) to specs/po #7582 Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-04/src/padding_metadata_leak_guard.rs (Rust, 1 function) to specs/po | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 29 total
fpga(coverage): line, toggle and FSM coverage as a t27 spec (Closes #7578) #7579 fpga(coverage): line, toggle and FSM coverage as a t27 spec (Closes #7578) | Created: 2026-10-07 | Updated: 2026-10-07 | 4 failing / 37 total
Port scripts/gen_w376.py (Python, 1 function) to specs/port/scripts/gen_w376.t27 #7568 Port scripts/gen_w376.py (Python, 1 function) to specs/port/scripts/gen_w376.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 29 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/db/queen-pool.ts (TypeScript, 3 functions) to specs/port/ #7567 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/db/queen-pool.ts (TypeScript, 3 functions) to specs/port/ | Created: 2026-10-07 | Updated: 2026-10-07 | 4 failing / 29 total
ci: test only the specs a change can affect -- t27c use-edges feeds specs/ci/affected.t27 (Closes #7565) #7566 ci: test only the specs a change can affect -- t27c use-edges feeds specs/ci/affected.t27 (Closes #7565) | Created: 2026-10-07 | Updated: 2026-10-08 | 4 failing / 40 total
Port scripts/gen_w369.py (Python, 1 function) to specs/port/scripts/gen_w369.t27 #7555 Port scripts/gen_w369.py (Python, 1 function) to specs/port/scripts/gen_w369.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 29 total
Port scripts/gen_w372.py (Python, 1 function) to specs/port/scripts/gen_w372.t27 #7554 Port scripts/gen_w372.py (Python, 1 function) to specs/port/scripts/gen_w372.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 4 failing / 29 total
Port gHashTag/trinity:src/depin/swarm_watch.zig (Zig, 2 functions) to specs/port/trinity/src/depin/swarm_watch.t27 #7553 Port gHashTag/trinity:src/depin/swarm_watch.zig (Zig, 2 functions) to specs/port/trinity/src/depin/swarm_watch.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 29 total
Port gHashTag/trios:tools/acm_ae_check/src/main.rs (Rust, 1 function) to specs/port/trios/tools/acm_ae_check/src/main.t2 #7552 Port gHashTag/trios:tools/acm_ae_check/src/main.rs (Rust, 1 function) to specs/port/trios/tools/acm_ae_check/src/main.t2 | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 29 total
Port fpga/verilog/gft_kat_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_kat_jtag.t27 #7540 Port fpga/verilog/gft_kat_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_kat_jtag.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 29 total
Port gHashTag/trios:crates/trios-trainer/src/data.rs (Rust, 7 functions) to specs/port/trios/crates/trios-trainer/src/da #7539 Port gHashTag/trios:crates/trios-trainer/src/data.rs (Rust, 7 functions) to specs/port/trios/crates/trios-trainer/src/da | Created: 2026-10-07 | Updated: 2026-10-07 | 5 failing / 29 total
t27b: which calls lower as the .len field, decided by lencall.t27 (Closes #7524) #7530 t27b: which calls lower as the .len field, decided by lencall.t27 (Closes #7524) | Created: 2026-10-07 | Updated: 2026-10-08 | 31 failing / 32 total
spec(numeric,math): the GoldenFloat lesson specs compile clean and say only true things #7496 spec(numeric,math): the GoldenFloat lesson specs compile clean and say only true things | Created: 2026-10-07 | Updated: 2026-10-08 | 9 failing / 32 total
fix(gen-c): a local nested array is declared as a C matrix (Closes #7441) #7495 fix(gen-c): a local nested array is declared as a C matrix (Closes #7441) | Created: 2026-10-07 | Updated: 2026-10-08 | 6 failing / 41 total
specs(port trios, browseros): unify LockGuard; rename 11 port-only types (Closes #7486) #7491 specs(port trios, browseros): unify LockGuard; rename 11 port-only types (Closes #7486) | Created: 2026-10-07 | Updated: 2026-10-08 | 3 failing / 30 total
specs(port compiler): unify AssembledInstr, LinkSection, LinkedSymbol, HirBoardResources; rename AsmSection, HwType (Closes #7485) #7490 specs(port compiler): unify AssembledInstr, LinkSection, LinkedSymbol, HirBoardResources; rename AsmSection, HwType (Closes #7485) | Created: 2026-10-07 | Updated: 2026-10-08 | 3 failing / 30 total
t27b: a test local named for a module var (Closes #7668) #7447 t27b: a test local named for a module var (Closes #7668) | Created: 2026-10-07 | Updated: 2026-10-08 | 0 failing / 4 total
t27core: for over one range and switch as a value, byte-identical to gen-c (Closes #7429) #7436 t27core: for over one range and switch as a value, byte-identical to gen-c (Closes #7429) | Created: 2026-10-07 | Updated: 2026-10-07 | 10 failing / 47 total
t27c: refuse a malformed number literal by name, read 0o as octal (Closes #7319, Closes #2645) #7421 t27c: refuse a malformed number literal by name, read 0o as octal (Closes #7319, Closes #2645) | Created: 2026-10-07 | Updated: 2026-10-07 | 14 failing / 43 total
gen-c: run defer at every exit of its block (Closes #7352) #7406 gen-c: run defer at every exit of its block (Closes #7352) | Created: 2026-10-07 | Updated: 2026-10-07 | 36 failing / 42 total
tri: test runs the tests; mutate plant names what a one-line mutant turns red #7400 tri: test runs the tests; mutate plant names what a one-line mutant turns red | Created: 2026-10-07 | Updated: 2026-10-07 | 4 failing / 37 total
t27b: an array length written as a constant expression (Closes #7347) #7382 t27b: an array length written as a constant expression (Closes #7347) | Created: 2026-10-07 | Updated: 2026-10-07 | 12 failing / 42 total

Summary

Status	Count
Total Open PRs	50
PRs with Failing Checks	43
PRs with All Checks Green	7
READY	2
FAILING	43
PENDING	0
NO CHECKS YET	0

These columns do not partition: 2 + 43 + 0 + 0 = 45, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

⚠️ STALE -- sha256(compiler.rs)=39fa3908f9fd != manifest seal=87e5cbd3ad94.
The committed NMSE numbers were certified against an older compiler.rs.
Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

gHashTag · 2026-10-08T12:44:35Z

The one red check, t27b-native-ratchet ("ratchet verdict red"), is red on master too: runs on 579bc55 and 1f2448e fail the same way. This PR touches no t27b code, only two fpga specs, their seals, the wrapper and XDC, and docs, so the failure is not this PR's. No fix exists in this PR's scope. The check is not required, and #7739 merged with it red.

Master moved (#7799 and #7802, neither touching t27b); the merge is clean. It is made on e6e8257 because the t27b lab is receipting that master, so the lane receipt can compare this head against it. The ledger keeps only this PR's two rows (zig_test_shadowing blocked -> pass, shadow_module_var new pass) on master's. Closes #7668 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

Brings master e6e8257 (t27-basics lessons #7799, AX7203 Ethernet beacon #7802) in. No conflict. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01ScHVrGSr6zZUdwkdC8DR9k

…) into the buses-course specs (Refs #7625) Brings master e6e8257 in. No conflict. Master adds specs/fpga/eth_beacon.t27 and rgmii_sniff.t27 beside this branch's eth_crc.t27 and rgmii.t27; the duplicate-body scan, the elaboration ratchet and the seal gates are re-run on the merged tree. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01ScHVrGSr6zZUdwkdC8DR9k

…ion baseline at 0 errors (Refs #7625) Master e6e8257 (#7802) added specs/fpga/eth_beacon.t27 and rgmii_sniff.t27 without baseline rows, so `python3 tools/check_elab_ratchet.py` fails on master itself ("NEW eth_beacon: 0 errors, not in baseline", same for rgmii_sniff), and fpga-build runs on this PR because it touches specs/fpga/. `--update-baseline` adds exactly those two rows, each at 0 errors (the strictest a row can be); no other row moves, total 177 -> 177. check_elab_ratchet.py: OK; --self-check and check_gate_preconditions.py pass; yosys read_verilog + hierarchy: 41/41. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01ScHVrGSr6zZUdwkdC8DR9k

gHashTag added the owner-approved-foreign Owner-approved exception to the only-t27 rule: hand-written foreign code allowed in this PR label Oct 8, 2026

gHashTag mentioned this pull request Oct 8, 2026

blog: an eye on the board -- a camera found the wrong board, a t27 beacon put the right one on the network gHashTag/trinity#1542

Closed

github-actions Bot mentioned this pull request Oct 8, 2026

Port bootstrap/src/compiler.rs lines 23970-24090 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/return_unsized #7797

Open

gHashTag mentioned this pull request Oct 8, 2026

blog: an eye on the board -- a camera found the wrong board, and a t27 spec put the right one on the network (Closes #1542) gHashTag/trinity#1543

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This was referenced Oct 8, 2026

specs(basics): the 27 t27-basics course lessons, upstreamed from trinity's vendored copy (Closes #7793) #7799

Merged

spec(queen): the event log as a bus, a cursor that loses nothing (Closes #7789) #7800

Merged

gHashTag enabled auto-merge (squash) October 8, 2026 12:24

github-actions Bot mentioned this pull request Oct 8, 2026

verified: R3-3 receipt from die A under t27c 0.5.1 (Closes #7815) #7816

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gHashTag merged commit e6e8257 into master Oct 8, 2026
29 of 30 checks passed

github-actions Bot mentioned this pull request Oct 8, 2026

t27b: .{} takes its result type, and a store of the fn's own frame address is refused, from t27 plans (Closes #7735) #7743

Merged

gHashTag mentioned this pull request Oct 8, 2026

queen(app): t27-bees as a CI/CD gate -- check runs, re-run, CI triage, merge queue #7834

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fpga: the bench board is an ALINX AX7203, and a t27 Ethernet beacon for it (Closes #7788) - #7802

fpga: the bench board is an ALINX AX7203, and a t27 Ethernet beacon for it (Closes #7788)#7802
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gHashTag commented Oct 8, 2026

The board is an ALINX AX7203

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