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Port gHashTag/trinity:fpga/uart_loopback_core.v (Verilog, 1 module) to specs/port/trinity/fpga/uart_loopback_core.t27 - #7095
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…ck_core.t27 Replaces the hand-written Verilog loopback core with a .t27 spec that the Verilog backend lowers. The generated module keeps the original name (uart_loopback_core) and data surface: - uart_rx in, packed result out: result[0] = uart_tx, result[1] = led - uart_loopback_tx mirrors uart_rx (assign uart_tx = uart_rx) - activity_led mirrors uart_rx (assign led = uart_rx) - clock fact: M22 @ 50 MHz (CLOCK_FREQ_HZ), UART D26/E26 (Bank 15) The Verilog backend gives a module one data output (result), so the two 1-bit outputs of the original travel packed: 3 = both high, 0 = both low. Five test blocks assert the loopback for both stimulus values, the port-order bundle, the packed result, and the board header facts. Closes #5668
A pull request must add exactly one docs/now entry and a bee has no way to know that: its brief names a boundary file and acceptance criteria, and docs/now/ is neither. The publisher adds it rather than failing the gate. Closes #5668 Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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Reviewer bee verdict for head e7c724e7eb7a4e9645ded7d0eea60f7c8bcf1edf (tools/bees/reviewer.py, zai glm-4.7-flash, glm-4.5-flash, 12 turns, 1369 s; then glm-4.7-flash, 3 turns, 236 s).
BEE-VERDICT: APPROVE
summary: Successfully ported UART loopback core from Verilog to T27 specification
criterion: "test -f specs/port/trinity/fpga/uart_loopback_core.t27 && echo present" -- met -- PASSED: prints present criterion: "grep -cE '^\s*(pub )?module uart_loopback_core\b' specs/port/trinity/fpga/uart_loopback_core.t27" -- met -- PASSED: prints 1
criterion: "t27c gen-verilog specs/port/trinity/fpga/uart_loopback_core.t27 | grep -cE '^module uart_loopback_core ?('" -- met -- PASSED: prints 1 criterion: "t27c spec-status specs/port/trinity/fpga/uart_loopback_core.t27 does not print NOPARSE" -- met -- PASSED: prints IMPLEMENTED
criterion: "grep -cE '^[[:space:]]*test[[:space:]]+("|[A-Za-z_])' specs/port/trinity/fpga/uart_loopback_core.t27" -- met -- PASSED: prints 5 criterion: "t27c test-report specs/port/trinity/fpga/uart_loopback_core.t27 2>&1 | grep -c BLOCKED" -- met -- PASSED: prints 0
discounted-check: spec-guards -- Already failing on master for the same reason (ledger drift in test blocks figure)
discounted-check: t27b-native-ratchet -- Already failing on master; verdict is based on corpus drift, not this specific change
Evidence
Based on my analysis, here's my review of pull request #7095:
Evidence
The port correctly implements the UART loopback core from the original Verilog:
- File creation:
specs/port/trinity/fpga/uart_loopback_core.t27was created (117 lines) - Module name: Contains exactly one module named
uart_loopback_coreas required - Generated Verilog:
t27c gen-verilogproduces a module with the same name - Parsing:
t27c spec-statusreturnsIMPLEMENTED(notNOPARSE) - Tests: Contains 5 test blocks covering all functions:
uart_tx_loopback- tests the loopback functionled_shows_data_activity- tests the LED functionoutput_bundle_in_port_order- tests the output structresult_packs_both_outputs- tests the bit packingboard_header_facts- tests the board constants
- No BLOCKED tests:
t27c test-reportreturns 0 BLOCKED tests - Boundary compliance: Only the specified file was modified
- Non-ASCII check: No non-ASCII identifiers found
The implementation correctly maps the original Verilog:
assign uart_tx = uart_rx→uart_loopback_tx()functionassign led = uart_rx→activity_led()function- Ports are split into input/output structs
- Results are packed into a single byte for the Verilog backend
Red checks analysis
Both red checks were already failing on master:
spec-guards: "on master: master fd28018: failure"t27b-native-ratchet: "on master: master fd28018: failure"
These are ledger/corpus count drifts that are unrelated to this specific port.
Second, independent review (glm-4.7-flash): APPROVE -- The change implements all acceptance criteria of #5668, adding a correct .t27 spec that parses, compiles, generates correct Verilog, and includes comprehensive tests.
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Closes #5668
Written by a bee on
queen-5668and published bytools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.🤖 Generated with Claude Code