fix(specs): five catalog-Broken t27 sources parse and generate (Closes #6437) - #6440
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…er takes examples/fpga/qmtech_minimal/design.t27 becomes module QmtechMinimalDesign (6 tests, 3 invariants, no pin table); specs/ar/datalog_engine.t27, specs/ar/ternary_logic.t27, specs/test_framework/graph_drift_detection.t27 and verilog_bench_harness.t27 drop Rust-only syntax. All five pass parse and the 7 backends with master t27c on the Railway lab; seals re-saved there. Closes #6437 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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This was referenced Oct 5, 2026
master red after #6440: corpus ratchet + specs_generate baseline still list the specs it fixed
#6452
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Oct 5, 2026
fix(specs): shrink the ledgers #6440 left behind; master ratchet green
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Closes #6437
Refs #6434
The SPECS catalog lists 59 gHashTag/t27 paths as Broken. I re-measured all 59 with master t27c (682564f) on the t27c Railway lab, running parse plus the 7 backends the catalog runs:
bootstrap/tests/[N][]const u8Fixes:
examples/fpga/qmtech_minimal/design.t27: was#-comment pseudo-config that no parser takes, with a pin table and part that disagree withfpga/HARDWARE_SSOT.md. It is now moduleQmtechMinimalDesign, carrying the heartbeat pattern, UART timing and resource budget.zig testpasses 6/6, and it has 3 invariants. Pins stay inspecs/boards/.specs/ar/datalog_engine.t27:loop { ... if > MAX { break } }becomeswhile iteration < MAX_STEPS, with the same iteration count.specs/ar/ternary_logic.t27: droppedtype Trit = Trit.specs/test_framework/graph_drift_detection.t27andverilog_bench_harness.t27:format!(becomesformat(,for (k, v) in m.nodesbecomesfor k in m.nodes.keys()plusget,if let Some(x) = m.get(k)becomescontains_keyplusget, andT?becomes?T.Verification (lab, master t27c): all 5 pass parse, gen, gen-c, gen-rust, gen-verilog, gen-verilog-hir, gen-js and gen-ts. Seals were re-saved with
t27c seal --save(PATH includes zig 0.16).qmtech_minimal_design.json(moduledesign) is replaced byqmtech_minimal_QmtechMinimalDesign.json.🤖 Generated with Claude Code