feat(t27b): f64 in AArch64 FP registers (Closes #6180) - #6286
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f64 + - * /, unary minus, comparisons, float literals, f64 params, results, locals and consts; @floatFromInt / @intFromFloat in Zig spelling with the result type from context. Arithmetic in d16/d17 (FADD/FSUB/FMUL/FDIV/FNEG/FCMP, SCVTF/UCVTF, FCVTZS/FCVTZU); AAPCS64 f64 arguments and results in d0-d7. Range-checked @intFromFloat traps on out-of-range values and infinities; NaN gives 0 as in Zig 0.16 Debug. Comptime floats fold only when exact (Zig folds comptime_float in f128). @sqrt and std.math.* stay rejected and named. No f32, no interpreter fallback. Outside the lane boundary: jit.rs marshals d0-d7 (call_fp); tests/blockers.rs used f64 as its example unsupported type, now f32. Closes #6180 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
# Conflicts: # cli/t27b/tests/differential.rs
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t27b compiles f64 in AArch64 FP registers (Closes #6180):
+ - * /, unary minus,== != < <= > >=, float literals, f64 params, results, locals and consts.@floatFromInt/@intFromFloatin Zig spelling, result type from context.@intFromFloattraps at a named site when out of range or infinite. A NaN gives 0. Checked against zig 0.16.0 withzig test: Debug panics on inf and returns 0 on NaN for every int width.comptime_float. Only literals that are exactly a double are folded. An inexact literal may only be coerced to f64 or compared; anything else is rejected with "Zig folds it in f128".@sqrtandstd.math.*stay rejected and are named (ExprCall(@sqrt)in--blockers). No f32. No interpreter fallback.Tests
tests/encoder.rsadds 22 encodings (129 -> 151 cases), under an ARM ARM C7.2 citation, each with the encoding fields it checks.eval.rscomputes f64 with the same IEEE ops as the JIT.f64_tests intests/differential.rscompare interpreter and JIT bit-for-bit. A disagreement panics; nothing is skipped.f64_arith_and_compare_match_interpreter,f64_conversions_match_interpreterandf64_mixed_arguments_and_calls_match_interpretercover edge values: signed zeros, infinities, quiet/signalling NaNs with payloads, subnormals, 2^53, and every int bound.f64_source_programs_run_in_both_enginesruns source programs, includinghalf(3.0) == 1.5.f64_refusals_name_the_constructchecks the refusals.t27c gen+zig test.cargo test -p t27b: all green.Outside the lane boundary (justified)
cli/t27b/src/jit.rs: the JIT entry has to load f64 arguments into d0-d7 and read d0 back (call_fp). The AAPCS64 requirement cannot be tested without this.cli/t27b/tests/blockers.rs: its fixture used f64 as the example of an unsupported type. It now uses f32, which is still unsupported.Corpus (
t27b corpus specs)t27c gen+zig test, with the same test counts. Files: base/debounce, benchmarks/gf16_bfloat16_nmse, conformance/e2e_scenarios, numeric/formats_catalog, physics/{e8_lqg_bridge, gamma-conflict, hslm_benchmark, lqg_cs_bridge}, port/fpga/verilog/e8m0_jtag, port/trinity/src/tri/{gen_aabb, gen_bezier, gen_quaternion, gen_rect}, the trios PH-01 and SC-00 libs, and trinet/etx.port/trinity/src/tri/gen_vector2d.t27Vec2_lengthfails because 5 Newton steps give 25.000000000167777, not 25.0. It fails underzig testas well, so the verdict matches.Top 5 of
--blockers(greedy, after the merge):Notes
strength_reducerewrites f64x * 2intox << 1, which does not compile. Until it is fixed, t27b refuses that shape asExprBinary(f64 * 2^k).t27b testprints the operands of a failed f64assert_eqas raw IEEE bits, as in the gen_vector2d line above.🤖 Generated with Claude Code