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fix(boards): correct Arty A7 FPGA pin and bank mappings - #5889

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dmitrii-f-t27 merged 4 commits into
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dmitrii-f-t27:codex/arty-a7-vendor-pins
Oct 4, 2026
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dmitrii-f-t27 merged 4 commits into
gHashTag:masterfrom
dmitrii-f-t27:codex/arty-a7-vendor-pins

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The Arty A7 profile passed assertions that encoded incorrect board pins. This fixes reset C12->C2, FPGA UART TX A9->D10 and RX C9->A9, LEDs R5/T5/T8/T9->H5/J5/T9/T10, and all12 placeholder I/O bank IDs. RX no longer shares a pin with button1. The vendor-backed tests now cover every modeled pin, bank, I/O standard and FPGA direction.

The UART mapping is resolved from Digilent's FPGA interface direction joined to its physical pin map; the Master XDC labels describe the USB bridge/PC viewpoint. Both35T/100T vendor mappings agree. Function bodies/API, logical port names and FPGA part constants remain unchanged. Original count_buttons coverage and all three commits from #5747 remain ancestors; its publisher receipt is retained.

Closes #5884. Closes #5722.

Validation:

  • TDD:12/23 new assertions fail against old constants;23/23 actual generated Zig tests and11existing compile-time invariants pass after correction. All5functions covered, zero typecheck errors/warnings.
  • Compiled Rust and regenerated declaration-only C drivers execute against both pinned vendor XML/XDC mappings:288scalar field comparisons and66pin-uniqueness pairs per backend. Five type-correct source mutants are rejected by actual Zig runtime assertions and the independent vendor/count oracle.
  • Compiler refreshes both existing seal aliases,23/23unforcedtests/allhashesMATCH; scoped seal validation passes. Fast corpus95/95CLEAN, types77/77CLEAN, duplicate-body gate unchanged, no expectation edits.

Limits: existing raw C string-assertion lowering still prevents full C compilation. The C SOURCE fixture replaces checks with a numeric sanity test, regenerates without editing generated files, and verifies declaration/type/function bytes match canonical output. Rust retains an existing parentheses warning. This is pin/bank metadata validation; no board, bitstream placement, timing, RF or complete inference is claimed. FPGA SKU/revision selection is a separate review.

Pinned vendor references and the execution receipt are in docs/now/2026-10-04-arty-a7-pins-match-vendor-constraints.md.

Trinity Bee and others added 4 commits October 3, 2026 10:10
A pull request must add exactly one docs/now entry and a bee has no way
to know that: its brief names a boundary file and acceptance criteria,
and docs/now/ is neither. The publisher adds it rather than failing the
gate.

Closes gHashTag#5722

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
tools/queen/publish.py wrote `(published DATE)`, which
tools/check_now_entry_shape.py HEADING does not accept; fixed in
the publisher by gHashTag#5777. Only the first line changes.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Closes gHashTag#5884. Closes gHashTag#5722.

Preserve original PR5747 history/count_buttons coverage; resolve FPGA UART viewpoint from vendor interface and pin-map evidence.
@dmitrii-f-t27
dmitrii-f-t27 merged commit 91abffe into gHashTag:master Oct 4, 2026
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Repair Arty A7 FPGA-facing pins and physical I/O banks Test the 1 untested function in specs/boards/arty_a7.t27

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