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Port gHashTag/trinity:fpga/openxc7-synth/d_lut_only.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_lut - #5499

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gHashTag merged 2 commits into
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queen-5495
Oct 2, 2026
Merged

gHashTag merged 2 commits into
masterfrom
queen-5495

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@gHashTag gHashTag commented Oct 2, 2026

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Closes #5495

Written by a bee on queen-5495 and published by tools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.

1 file changed, 153 insertions(+)

🤖 Generated with Claude Code

Trinity Bee and others added 2 commits October 2, 2026 00:59
…ation

- Create specs/port/trinity/fpga/openxc7-synth/d_lut_only.t27
- Implement trinity_top module with LUT-only inverter logic
- LED = ~clk (direct LUT implementation)
- Add comprehensive tests and validation
- Include invariants and benchmarks

Closes #5495
A pull request must add exactly one docs/now entry and a bee has no way
to know that: its brief names a boundary file and acceptance criteria,
and docs/now/ is neither. The publisher adds it rather than failing the
gate.

Closes #5495

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
@gHashTag
gHashTag enabled auto-merge (squash) October 2, 2026 01:10
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📓 NotebookLM Notebook linked to this PR

This notebook contains session context, decisions, and artifacts for this work.

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PR Dashboard

Generated at: 2026-10-02 01:10:38 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 46
PRs with All Checks Green 4
READY 3
FAILING 46
PENDING 0
NO CHECKS YET 0

These columns do not partition: 3 + 46 + 0 + 0 = 49, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=b7d5cc5c4cf1 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@gHashTag
gHashTag merged commit f5fe09b into master Oct 2, 2026
25 of 31 checks passed
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Port gHashTag/trinity:fpga/openxc7-synth/d_lut_only.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_lut_only.t27

2 participants