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Port gHashTag/trinity:fpga/openxc7-synth/d6_inv_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d6_i - #5446
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Create specs/port/trinity/fpga/openxc7-synth/d6_inv_test.t27 as a module trinity_top that describes the original Verilog's behavior. The original module has: - input wire clk - output wire led - assign led = 1'b1 (constant high output) The T27 implementation includes: - ClockSignal and LedSignal structs - Functions to compute LED output (always high) - Comprehensive tests for all functions - Validation and invariants - Benchmarks for performance Closes #5442
A pull request must add exactly one docs/now entry and a bee has no way to know that: its brief names a boundary file and acceptance criteria, and docs/now/ is neither. The publisher adds it rather than failing the gate. Closes #5442 Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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October 1, 2026 14:50
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Closes #5442
Written by a bee on
queen-5442and published bytools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.🤖 Generated with Claude Code