docs(now): re-date the source-kind entry into the review window

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NotebookLM Gate on: push 1

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Issue Gate on: pull_request_target 2

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NotebookLM Auto-Sync on: pull_request 4

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manual-sync

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NotebookLM Gate on: pull_request 1

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Documented Commands on: pull_request 2

Documented t27c subcommands exist

Duplicate Body Ratchet on: pull_request 1

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PR Dashboard on: pull_request 1

pr-dashboard

Damage Negatives on: pull_request 2

Damage negatives (false-positive fixtures)

Withdrawn Number Gate on: pull_request 2

withdrawn-live

Untrusted Input Gate on: pull_request 2

untrusted-input

Orphaned modules on: pull_request 2

Every source file is reachable from its crate root

Check Now Freshness on: pull_request 1

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Harness scratch directories on: pull_request 2

No test binary shares one scratch directory

Gate Topology on: pull_request 1

gate-topology

L1 TRACEABILITY Check on: pull_request 3

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L1 Traceability Summary

Schema Validation on: pull_request 2

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FPGA E2E Build on: pull_request 16

fpga-smoke

fpga-lint (read_verilog + hierarchy)

fpga-synthesis

fpga-synthesis-arty

fpga-formal

fpga-conformance

fpga-bitstream

fpga-report

cli-tri on: pull_request 3

cli-tri

Spec Parse Ratchet on: pull_request 2

parse-ratchet

Emit Bit-Exact Gate (CI-02) on: pull_request 3

emit-bitexact

Seal Coverage on: pull_request 2

coverage

NOW Sync Gate on: pull_request 1

check-now-freshness

Bootstrap Test Ratchet on: pull_request 5

test-ratchet

Spec Guards on: pull_request 3

spec-guards

Conflict Markers on: pull_request 2

Conflict markers (no unresolved merges)

secret-scan on: pull_request 1

scan

Corpus Ratchet on: pull_request 2

Corpus ratchet (expected-failure ledger)

PHI Loop CI on: pull_request 1

phi-loop-check

Verilog Widths on: pull_request 2

Verilog widths (absurd-width ledger)

NotebookLM Auto-Sync on: pull_request_review 3

extract-issue

sync-activity

manual-sync

sync-notebook

NotebookLM Auto-Sync on: pull_request 4

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