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t27b verilog: pin attributes on ports -- a board top carries its own pinout (Closes #10199) - #10209
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…/_SLEW/_IN_TERM) Refs #10170 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…re no pin or port Refs #10199 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…pin attribute Refs #10199 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…g_pin_attrs Refs #10199 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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… master (Closes gHashTag#8889) Master gained pin attributes for t27b verilog while this PR was open (gHashTag#10209, gHashTag#10170: a str const `<port>_LOC` / `_IOSTANDARD` / `_SLEW` / `_IN_TERM` becomes `(* KEY = "value" *)` on that port; tested by specs/tri/t27b/conformance/verilog_pin_attrs.t27). That is the same feature as this PR's `<port>_PIN` / `_IOSTANDARD` / `_SLEW` declarations, with the same function names (pin_decl, put_pins, pin_named) in verilog_emit.t27, so the two cannot both stay. Per the DRY rule the master mechanism is kept as the one implementation and this PR's copy is dropped: - specs/tri/t27b/verilog_plan.t27, verilog_emit.t27, their gen/rust files and their two seals: master's version, byte for byte. - specs/trinet/eth_top_ax7203.t27: the 22 `<port>_PIN` consts become `<port>_LOC` (same pin values, same IOSTANDARD and SLEW); comments name gHashTag#10170. `t27b verilog` writes 22 ports with LOC / IOSTANDARD / SLEW attributes, 13 instances, 3 t27_period_ps attributes. - specs/physics/xc7_primitives.t27 (IBUFDS, PLLE2_ADV, ODDR, BSCANE2 DRCK): unchanged by master, merged as is. - docs/reports/t27b_expectations.json: master's rows plus this PR's eth_top_ax7203 row, in path order. - .trinity/seals/trinet_TrinetEthTop.json: saved again (spec changed). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Closes #10199. Refs #10024, #10170 (option A, step 2: the DDR3 head-bandwidth top).
A board top written in t27 can now carry its own pinout.
t27b verilogwrites each pin's placement and I/O standard as Verilog attributes on the port; yosys keeps them and nextpnr-xilinx reads them. No constraint file is written by hand. The parser does not change. Everything hand-written is .t27; the Rust undergen/is regenerated byt27c gen-rust.constwhose value is a string literal, named<port>_<KEY>with KEY one ofLOC,IOSTANDARD,SLEW,IN_TERM, is written as(* KEY = "value" *)before that port.clk/rst_n/en, an unboundon_clockparameter, an input, an inout, and an output (reg or wire).verilog_plan.t27(pin_key,is_pin_name,pin_kind,declares_pin). The writing is inverilog_emit.t27(is_str_const,pin_decl,put_pins,is_port,pin_named).z_LOC"). Otherwise a misspelt pin would leave its port to the placer without a word.specs/tri/t27b/conformance/verilog_pin_attrs.t27. It puts pins on the implicitclk, anon_clockparameter (btn) and apub var(led).Evidence (Railway lab, x86_64, branch at 25b9ead plus the regenerated files)
Test reports. Each has 0 vacuous passes:
verilog_plan.t27verilog_emit.t27verilog_pin_attrs.t27New tests:
a_pin_attribute_is_named_by_its_port_and_key(plan, 11 asserts)a_pin_attribute_rides_on_the_port_it_names(emit). It checks the exact port text for an input and an output, the refusal for a pin that names no port, a non-string literal, and an empty name.gen-rust. Both files are deterministic: two runs are byte-identical.
t27bbuilds with them.t27b verilogon the conformance spec writes, for example:Yosys (
read_verilog; write_json): theclk,btnandledports keepLOC,IOSTANDARDand (onled)SLEW.Negative control. The conformance spec with
btn_LOCrenamed tobtm_LOCexits 2 with "unsupported construct pin attribute for no port of the modulebtm_LOC". The line number in that message is 0: the glue gives a module-level const no source line. The name is what identifies it.Mutation controls. Each mutation is applied to the spec, then the test report is run. All 8 are killed:
declares_pinremoved_separator check removedca + s + 2to+ 1)"Separator check removed" survived at first. The test's no-separator name was 4 characters, so the length check rejected it first. A 5-character
xyLOCnow kills it.Corpus diff. The master
t27band the brancht27beach ranverilogon all 2,220 specs underspecs/, and stdout, stderr and exit codes were compared. 2,219 are identical. The one that differs is the newverilog_pin_attrs.t27(exit 0 on both).Seals. Resealed:
t27b_T27bVerilogPlant27b_T27bVerilogEmitconformance_T27bConformanceVerilogPinAttrsLedger.
docs/reports/t27b_expectations.jsongains the rowverilog_pin_attrs.t27: pass.Not verified here
t27b nativeratchet in CI checks.🤖 Generated with Claude Code