Added a ThreadX module manager port for the Cortex-R52

ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/cache.c

@@ -0,0 +1,149 @@
+/***************************************************************************
+ * Copyright (c) 2026 Eclipse ThreadX contributors
+ *
+ * This program and the accompanying materials are made available under the
+ * terms of the MIT License which is available at
+ * https://opensource.org/licenses/MIT.
+ *
+ * AI Disclosure: This file was largely AI-generated by Claude Code (Opus 5).
+ * The AI-generated portions may be considered public domain (CC0-1.0)
+ * and not subject to the project's licence. The human contributor has
+ * reviewed and verified that the code is correct.
+ *
+ * SPDX-License-Identifier: MIT and CC0-1.0
+ **************************************************************************/
+
+/**************************************************************************/
+/*                                                                        */
+/*  BOARD SUPPORT                                          RELEASE        */
+/*                                                                        */
+/*    cache.c                                          Cortex-R52/GNU     */
+/*                                                           6.5.2        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Frédéric Desbiens, Eclipse Foundation                               */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    Cache maintenance for a loader that copies code.  See cache.h for    */
+/*    why only these three functions exist.                               */
+/*                                                                        */
+/*  MISRA C:2012 deviations (justified)                                   */
+/*                                                                        */
+/*    Directive 4.3 -- cache maintenance and CTR are reachable only        */
+/*      through CP15; every access is encapsulated in a one-line accessor  */
+/*      below and nowhere else in this file.                              */
+/*    Rule 11.6 (conversion between a pointer and an integer) -- a cache   */
+/*      maintenance operation takes a virtual address as a register value, */
+/*      so the conversion is what the instruction requires.               */
+/*                                                                        */
+/**************************************************************************/
+
+#include "cache.h"
+
+/* The smallest data-cache line in the machine, from CTR.DminLine.  Held as a
+   log2 of the number of 32-bit words, so the byte count is 4 << DminLine.
+   DminLine and not the L1 geometry: a maintenance-by-address walk has to step
+   by the smallest line any level implements, or it skips lines in that level. */
+
+#define CTR_DMINLINE_SHIFT      16U
+#define CTR_DMINLINE_MASK       0xFUL
+
+
+/**************************************************************************/
+/*  CP15 accessors.  The only assembly in this file (MISRA C:2012 Dir 4.3).*/
+/**************************************************************************/
+
+static unsigned long read_ctr(void)
+{
+    unsigned long value;
+    __asm__ volatile("mrc p15, 0, %0, c0, c0, 1" : "=r"(value));
+    return value;
+}
+
+static void clean_dcache_line(unsigned long address)
+{
+    __asm__ volatile("mcr p15, 0, %0, c7, c10, 1" :: "r"(address) : "memory");
+}
+
+static void invalidate_icache_all_op(void)
+{
+    unsigned long zero = 0UL;
+    __asm__ volatile("mcr p15, 0, %0, c7, c5, 0" :: "r"(zero) : "memory");
+}
+
+static void data_sync_barrier(void)
+{
+    __asm__ volatile("dsb sy" ::: "memory");
+}
+
+static void instruction_barrier(void)
+{
+    __asm__ volatile("isb" ::: "memory");
+}
+
+
+/**************************************************************************/
+/*  cache_dcache_line_bytes                                               */
+/**************************************************************************/
+
+unsigned long cache_dcache_line_bytes(void)
+{
+    return 4UL << ((read_ctr() >> CTR_DMINLINE_SHIFT) & CTR_DMINLINE_MASK);
+}
+
+
+/**************************************************************************/
+/*  cache_clean_range                                                     */
+/*                                                                        */
+/*  Clean by virtual address over [start, start + length).                 */
+/*                                                                        */
+/*  The start is rounded DOWN to a line boundary and the walk continues    */
+/*  past the end until the last line containing a requested byte has been  */
+/*  cleaned.  Rounding the start up instead would leave the first partial  */
+/*  line dirty, which is the whole failure this exists to prevent and is    */
+/*  invisible whenever the caller happens to be line aligned.              */
+/**************************************************************************/
+
+void cache_clean_range(const void *start_address, unsigned long length)
+{
+    unsigned long line = cache_dcache_line_bytes();
+    unsigned long address;
+    unsigned long end;
+
+    if (length == 0UL)
+    {
+        return;
+    }
+
+    address = (unsigned long) start_address;
+    end     = address + length;
+
+    address &= ~(line - 1UL);
+
+    while (address < end)
+    {
+        clean_dcache_line(address);
+        address += line;
+    }
+
+    /* The stores have to be complete before anything fetches from the range. */
+
+    data_sync_barrier();
+}
+
+
+/**************************************************************************/
+/*  cache_invalidate_icache_all                                           */
+/**************************************************************************/
+
+void cache_invalidate_icache_all(void)
+{
+    invalidate_icache_all_op();
+
+    /* DSB then ISB: the invalidate must complete, and the pipeline must be
+       flushed of anything fetched before it did.  */
+
+    data_sync_barrier();
+    instruction_barrier();
+}

ports/cortex_r52/gnu/example_build/fvp_baser_aemv8r/cache.h

@@ -0,0 +1,72 @@
+/***************************************************************************
+ * Copyright (c) 2026 Eclipse ThreadX contributors
+ *
+ * This program and the accompanying materials are made available under the
+ * terms of the MIT License which is available at
+ * https://opensource.org/licenses/MIT.
+ *
+ * AI Disclosure: This file was largely AI-generated by Claude Code (Opus 5).
+ * The AI-generated portions may be considered public domain (CC0-1.0)
+ * and not subject to the project's licence. The human contributor has
+ * reviewed and verified that the code is correct.
+ *
+ * SPDX-License-Identifier: MIT and CC0-1.0
+ **************************************************************************/
+
+/**************************************************************************/
+/*                                                                        */
+/*  BOARD SUPPORT                                          RELEASE        */
+/*                                                                        */
+/*    cache.h                                          Cortex-R52/GNU     */
+/*                                                           6.5.2        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    Frédéric Desbiens, Eclipse Foundation                               */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    The cache maintenance a loader owes the instruction side, and        */
+/*    nothing else.                                                       */
+/*                                                                        */
+/*    The S32Z280 board support carries a full cache driver -- enable,     */
+/*    disable, geometry, set/way sweeps -- because silicon bring-up needed  */
+/*    to ask the hardware what it had.  None of that is needed here: the    */
+/*    caches are turned on once in mpu_init and never turned off, and the   */
+/*    model's geometry is not in question.  What IS needed is the pair of    */
+/*    operations that make copied code executable, so that is all this is.  */
+/*                                                                        */
+/*    Why it is needed at all: the module area is Normal write-back memory, */
+/*    so a byte copy of module code leaves the bytes in dirty data-cache    */
+/*    lines while the instruction side -- which is not coherent with the    */
+/*    data cache on this core -- fetches whatever main memory still holds.   */
+/*    Cleaning by address range and then invalidating the instruction cache  */
+/*    is what closes that gap.                                             */
+/*                                                                        */
+/*    By range rather than by set/way, deliberately.  A set/way sweep needs */
+/*    the cache geometry and touches every line in the machine; the loader   */
+/*    knows exactly which bytes it wrote, so the range form is both tighter  */
+/*    and shorter to get right.                                             */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef CACHE_H
+#define CACHE_H
+
+/* Clean (write back) the data cache over one address range, so that main
+   memory holds what the copy wrote.  Rounds outwards to cache-line
+   boundaries; a length of zero does nothing.  */
+
+void cache_clean_range(const void *start_address, unsigned long length);
+
+/* Invalidate the whole instruction cache, so no stale line from a previous
+   image at the same address can be served.  Invalidate-all rather than by
+   range because it is one register write and this runs once per load.  */
+
+void cache_invalidate_icache_all(void);
+
+/* Data cache line length in bytes, from CTR.DminLine.  Published because the
+   range walk above depends on it and a caller may want to report it.  */
+
+unsigned long cache_dcache_line_bytes(void);
+
+#endif /* CACHE_H */